ACD Atlas Computing Division Prime Computer Systems

Jump To Main Content

Jump Over Banner

Home

ACDICFMulti User MinisPrime

Jump Over Left Menu

Prime 750

PR1ME Product Bulletin: Prime 750 System

DESCRIPTION

The Prime 750 is the most powerful member of Prime's new family of hardware- and software-compatible systems. With many features that fully exploit its 32-bit architecture, the 750 offers speed, low overhead, and flexibility in a wide range of computational timesharing and interactive data processing applications.

Key contributors to the Prime 750's speed and low overhead are a 16K-byte cache memory, instruction prefetch unit, high-bandwidth burst mode I/O, and interleaved main memory. In addition, a high-performance floating-point unit provides instruction execution speeds that rival systems costing much more. This feature, along with a 32 million-byte virtual address space for programs, makes the 750 a fast and powerful tool in scientific and engineering applications.

For commercial applications, the Prime 750 offers COBOL program execution speed exceeded by no system short of a mainframe. Especially in environments requiring the flexibility to use other languages, and add users and applications, the 750 outperforms any system in its price range.

Programs written for any Prime system run without modification on the 750. And since it is compatible with all Prime peripherals, controllers, and I/O interfaces, any Prime system can be upgraded to a 750 at a fraction of the total system cost and with minimal conversion effort.

FEATURES

PRIME 750: MINICOMPUTER RESPONSIVENESS AND MAINFRAME CAPABILITY

The Prime 750 integrates the proven attributes of the previous top-of-the-line system, the Prime 500, with many new features that optimize its 32-bit internal architecture. The result is an exceptionally fast, responsive computer system with mainframe functionality. Yet, the Prime 750 is both affordable and totally compatible with its predecessors.

At the heart of the 750's speed are a high-capacity cache memory, instruction prefetch buffer, burst mode I/O, interleaved main memory, and a high-performance floating-point unit. Its efficient microcode structure ensures high-speed instruction execution. The number of microcode steps, as well as the time required for each step in an instruction execution cycle, are significantly lower than other systems. The 750, for example, completes a 32-bit register memory add instruction in but one machine cycle (micro-step).

The Prime's 750's mainframe-level capabilities are a derivative of PRIMOS, the uniform operating system for all Prime computers. With PRIMOS, the 750 can perform timesharing for up to 63 users, multi-tasking, and batch operations. Each user has a 32 million byte virtual address space and a variety of languages that simplify programming.

HIGH PERFORMANCE, LOW OVERHEAD

Four facilities contribute to the Prime 750's speed and efficiency: a high-capacity cache memory, an instruction prefetch unit, burst mode I/O, and interleaved main memory.

Cache Memory

With a 16K-byte capacity, the Prime 750 cache memory dramatically reduces instruction execution times and processor overhead. This high-speed (80 nanosecond access) bipolar memory decreases the effective memory cycle time to near that of the processor by storing the information that most likely will be used next by the processor. Its high capacity provides a 95 per cent hit rate on anticipated processor requirements.

Both the instruction prefetch unit and the central processor's execution unit access cache memory. Cache is located on the central processor, rather than on main memory boards, thereby eliminating memory bus delays in cache-to-processor transfers. Memory mapping and cache memory usage completely overlap, further reducing execution time and central processor administrative overhead.

Instruction Pre fetch Unit

The instruction prefetch unit improves central processor performance by both prefetching and decoding up to four instructions from cache memory. Because it accesses cache independently of the central processor, it prefetches, decodes, and forms the effective address in parallel with instruction execution. Therefore, when the processor's execution unit is ready for the next sequential instruction, the instruction is prepared for execution in advance. This means the Prime 750 spends more time executing and less in time-consuming administrative overhead.

Control logic in the instruction prefetch unit continuously fetches data from cache to keep its buffer full. In addition, the instruction prefetch unit can resolve most indirect addresses, further increasing instruction execution speed.

Memory Cache Memory Instruction Prefetch Unit Processor Execution Unit Effective Address

Figure 1: The instruction prefetch unit accesses cache memory independently of the central processor to perform instruction prefetch and decoding in parallel with execution.

Effective Address

Figure 1: The instruction prefetch unit accesses cache memory independently of the central processor to perform instruction prefetch and decoding in parallel with execution.

Burst Mode I/O

The Prime 750 uses an I/O mode that increases throughput and reduces central processor overhead. Called burst mode I/O, it provides an 8 million-byte-per-second transfer rate over the interface between the processor and peripheral controllers. This high bandwidth channel reduces the central processor's I/O load, and enhances the performance of high-speed peripherals.

The Prime 750 supports direct-to-memory I/O operations with four types of access modes: Direct Memory Access (DMA), Direct Memory Control (DMC), Direct Memory Transfer (DMT), and Direct Memory Queue (DMQ).

The 750 has 32 DMA channels, controlled by high-speed channel address registers, which support an 8 million-byte-per-second transfer rate using burst mode I/O. High-speed peripherals such as disk subsystems typically use these channels.

DMC channels, controlled by channel address words in the first 8K-bytes of virtual memory, offer up to 2048 channels for medium-speed I/O transfers such as those in serial data communications. Their maximum transfer rate is 960K bytes per second.

DMT handles channel programs for high-speed device controllers, such as the controllers for moving-head disks. Its maximum throughput rate is 2.5 million bytes per second.

In addition, DMQ channels provide circular queues for handling communication devices. These queues reduce operating system overhead by eliminating interrupt handling on a character-by-character basis.

Interleaved Main Memory

The Prime 750, like all other Prime systems, uses MOS main memory exclusively. It can address up to 8 million bytes of ECC main memory, and reduces main memory access time to near that of the central processor through the use of the 16K-byte cache memory.

Because consecutive memory locations are on separate memory boards, interleaving can be used to speed-up sequential memory accesses and maximize the cache hit rate. In effect, interleaving provides high-speed transfers between memory and the central processor by allowing the processor to read or write four bytes at a time. During burst mode I/O, interleaving provides 64-bit data transfers for optimum performance of high-speed disks and magnetic tape subsystems.

In addition to 32-bit transfers and 64-bit interleaving, the 750 supports 16-bit transfers for I/O devices and controllers that use this format, as well as half-word instructions such as a 16-bit WRITE. This preserves existing investments in peripheral equipment and maintains total compatibility of programs.

VIRTUAL MEMORY MANAGEMENT

The Prime 750's virtual memory management facilities simplify program sharing and give users a powerful 32 million-byte virtual address space for programs. This lets programmers write large programs that can execute in both small and large main memory configurations with no need to define overlays or later modify programs to take advantage of additional memory.

Memory management facilities provide each system user with a private and shared system address space. Through segmentation and paging, this space is divided into 128K-byte segments, of which 256 segments (32 million bytes) are available for each user, and the rest for shared operating system software. By embedding operating system functions in each virtual memory space, all operating system functions are immediately available as if they were an integral part of a user's program, dramatically reducing system overhead.

School's Project Prime 750

School's Project Prime 750
Large View

FAST, FLEXIBLE COMPUTATION

The Prime 750 gives users the flexibility to perform a variety of arithmetic operations on three generic data types: floating-point, decimal, and integer. Its new floating-point unit provides execution speeds comparable to much more expensive systems. With the expanded business instruction set, the 750 offers very fast decimal arithmetic. It provides fast integer arithmetic with a 32-bit unit built to support system architecture. And its basic instruction set includes many capabilities that are typically a part of the operating system or are subroutines in other computers - for example, queue handling, parameter passing, and conditional branching.

These microcode-implemented facilities are designed to optimize PRIMOS, the compilers supported by PRIMOS, and the system's 32-bit architecture. The result is speed and simplicity in accessing system resources, manipulating data, and program control.

Floating-point Arithmetic

With the Prime 750, users can expect floating-point performance that exceeds much more expensive systems. Its double-precision throughput ranks among the highest in the industry. And in timeshared, multilingual environments, the Prime 750 far surpasses the floating-point performance of any system in its price range.

A new floating-point unit that optimizes the 750's 32-bit architecture is the major contributor to this performance. With a 32-bit path between the unit and central processor, the unit can accept data at an extremely fast rate. Registers assigned to floating-point operations are integral to the unit itself. Its use of parallel logic permits exponential and fractional calculation to be done simultaneously, still another reason for its speed. Separate parallel logic performs binary multiplication four bits at a time, division three bits at a time, and addition 48 bits at a time.

Business Instructions

The Prime 750 provides high-level support for ANSI'74 COBOL with comprehensive instructions designed for decimal arithmetic, character field manipulation, and editing operations. Compared with even the impressive COBOL performance of the previous top-of-the-line Prime 500, it increases COBOL throughput by a factor of two.

COBOL decimal arithmetic operations support packed or unpacked signed numbers of up to 18 digits. Operands differing in data type and/or scale factor are handled automatically during add, subtract, multiply, divide, and comparison operations. Business instructions also allow rounding on numeric operations, and provide for binary-to-decimal and decimal-to-binary conversions.

Character operations can be applied to field sizes of virtually any length. Justification, truncation, and padding are automatic in move, compare, translate, edit, and similar operations. Numeric and character editing instructions let the user easily produce fields in ANSI'74 COBOL picture-like formats. For maximum efficiency, all business operations involve a limited number of in-line instructions.

High-speed Integer Arithmetic Unit

All integer arithmetic and logical operations are performed in the processor's 32-bit arithmetic unit. By using a 32-bit format, the Prime 750 significantly improves the execution times of integer arithmetic instructions. The design of the arithmetic unit also permits efficient handling of complex formation, such as base-plus-displacement and indexing.

Standard Instruction Set

The standard instruction repertoire is a compatible superset of the machine instructions available with previous Prime systems. Its addressing mode compatibility allows user programs written for any multi-user Prime system to run without modification on the 750.

Over 300 instructions provide enhanced operating system communication, data handling, and cooperation of processes. Highly flexible address formation techniques allow all instructions to use any of four user-accessible base registers, up to seven index registers, and 32-bit indirect words in any combination. Thus, all memory reference instructions can access any datum in the entire virtual address space.

The Prime 750 features instruction capabilities that exploit the system's 32-bit memory and cache data paths, and 32-bit internal architecture. Of its eight 32-bit general purpose registers, seven can be used as index registers. These registers also can be used in local storage for compiler optimization and as fixed-point and logical accumulators. There are two floating-point registers, each 64 bits long, and two field address and length registers used by character and decimal instructions, also 64 bits long. Four other 32-bit registers include a procedure base, stack base, link base. and auxiliary base register.

SYSTEM ARCHITECTURE

Prime was the first company to put software first in the natural order of engineering. The Prime 750 is an extension of that philosophy because its hardware is designed to complement system software. For example, the 750's program environment, control and scheduling facilities, and resource allocation mechanism operate within the framework of the PRIMOS operating system. The result is a system that decreases the cost of computing and increases application flexibility.

Uniform System Software

A single, uniform operating system, PRIMOS, lets all Prime systems peform multi-terminal, batch, and multi-task operations. Because PRIMOS is embedded in each user's virtual memory space, it ensures fast program access to operating system resources. It supports re-entrant procedures, permitting a single copy of a software module, such as the text editor or FORTRAN compiler, to be shared by many users. PRIMOS further supports ANSI '74 COBOL, ANSI'77 FORTRAN, BASIC, BASIC/VM, RPG II, PL/1, Prime Macro Assembler, the source-level debugger, and the various levels of query facilities provided by PRIME/POWER; DBMS, Prime's CODASYL-compatible Database Management System; MIDAS, the Multiple Index Data Access System; FORMS, the Forms Management System; and a wide variety of application packages available from the Prime Users Library Service (PULSE), from other users, and from third party vendors.

Stack Architecture

Prime 750 programs operate in a multi-segment environment including a stack segment that contains all local variables; an instruction or procedure segment, and a linkage segment that contains statically allocated variables and linkages to common data. Highly efficient addressing modes provide access to stack and linkage variables. Hardware-implemented CALL and RETURN instructions eliminate the overhead of software stack management routines. The 750's stack architecture optimizes the efficiency of operations such as parameter passing, subroutine and procedure calls, arithmetic expression evaluation, and dynamic allocation of temporary storage.

Process Exchange

A process exchange facility automatically transfers the central processor's attention from one activity (process) to another, with minimum overhead and complete protection. It allocates resources to the highest priority process in a series of tasks awaiting execution in a queue. It further handles the logistics of processes ready for execution and those waiting for a specific event to occur. The process exchange facility includes firmware that automatically dispatches a task for execution and reorders those remaining without software intervention.

Register Sets

The Prime 750 has 128, 32-bit hardware registers divided into four sections. One 32-register section handles firmware and operating system functions. The second section controls the processor's 32 high-speed Direct Memory Access (DMA) channels. The remaining two sections hold the machine states of active processes. The process exchange facility manages register assignment to processes dynamically and automatically.

SYSTEM INTEGRITY

The Prime 750 provides system integrity through comprehensive error detection and reporting mechanisms. Micro-verification routines are invoked automatically when the system is initialized. These routines test the validity of the CPU logic and indicate the cause of any malfunction via a diagnostic status word.

While the system is running, parity checking ensures data integrity throughout the processor's internal busses, registers, and other data paths. In addition, the 750 automatically checks the parity of each microcode control word. Error-correcting code in real memory automatically detects and corrects all single-bit errors, making them totally transparent to the users. All two-bit errors are reported as well.

The Prime 750 also includes a comprehensive, hardware-controlled memory protection system. A multi-ring protection hierarchy allows programs to be assigned to any of several security levels. Thus, multiple users can have full access to specified programs, while other programs and databases are protected against unauthorized access, and operating system software is guarded against accidental user intrusion.

MAXIMUM UPTIME WITH EASY REMOTE DIAGNOSTICS

The Prime 750 includes a sophisticated Virtual Control Panel (VCP). It allows a diagnostic specialist to remotely control any system. This provides users with fast, effective troubleshooting-whether the task is identifying a hardware problem or installing a new revision of the operating system.

The system administrator permits remote access by simply pushing a button. A second button provides one of two modes of remote access: the remote terminal can be placed in monitor mode only, or be given the capability to operate as if on-site.

The VCP displays the state of the remote communications link via two indicator lamps mounted on the cabinet. One lamp indicates that the administrator has given a remote user the ability to dial into the system. And the second lamp indicates whether or not a remote access is in progress. If this lamp is flashing, the remote user has been given the same control as the system administrator.

DISTRIBUTED PROCESSING WITH PRIME SYSTEMS

The Prime 750, 650, and 550 support distributed processing with an array of software and hardware communications products. PRIMENET, Prime's networking software, lets Prime computers communicate among themselves, with terminals, and with other manufacturers' systems over low-cost packet switching networks. Users can interface Prime computers to a variety of terminals and communications lines with multiple protocols and remote job entry options: IBM BISYNC for HASP and 2780; High-level Data Link Control (HDLC) protocol for X.25 packet switching networks; Control Data 200UT; Univac 1004; and ICL 7020. Prime's Distributed Processing Terminal Executive (DPTX) software conforms to protocols used by IBM 3271/3277 Display Systems. And Prime offers hardware controllers for both synchronous and asynchronous communications.

PRIME Computer Inc.,
40 Walnut Street,
Wellesley Hills,
MA 02181

Sales and service offices in major U.S. cities with subsidiaries in Denmark, Federal Republic of Germany. France. Norway, Sweden, and the United Kingdom; distributors in Australia, Austria, Canada. Ecuador, Greece, Italy, Japan, Korea. The Netherlands, New Zealand. Saudi Arabia, Singapore. and Switzerland.