The main parts of Atlas 1 consist of:-
2.1.1 The control unit produces in correct sequence the control signals necessary to call for an instruction, to decode it, to modify the address, to obtain the operand from store and to perform the arithmetic operation. The address of the current instruction is held in one of three special index registers, called control registers. Before the current instruction is decoded the contents of the control register in use are increased by one in anticipation of the next instruction.
2.1.2 Arithmetic is mainly done in the accumulator, which is a double-length floating-point register. The accumulator arithmetic unit can obey 49 different instructions, including different types of addition, subtraction, multiplication and division, transfers, tests, shifts etc.
For small integer arithmetic, modification and counting, there are also 128 index registers. These are known as B-registers and have their own arithmetic unit. The B-register arithmetic unit can obey 51 different instructions, including addition, subtraction, logical operations, shifts, tests, counts etc.
2.1.3 Any peripheral transfer on Atlas 1 has only to be initiated, after which it proceeds independently, leaving the central computer free to continue obeying instructions. Suppose there to be only one program in the computer, which might be reading characters from the tape reader and sorting them on magnetic tape, one per word in units of 512 words. The tape reader operates at 300 characters per second and so reads a character once every 3,333 microseconds (µs); a magnetic tape transfer of 512 words takes 46 milliseconds (ms). Between reading characters it would be possible for the central computer to obey about 2,000 instructions, and while executing a magnetic tape transfer, about 30,000 arithmetic instructions could be obeyed. If the computer were to be idle during transfers because the information was wanted immediately (in the next instruction) obviously its utilisation would be very inefficient. Note that if the slow. peripheral equipments could always transfer information at the rate required by the central computer for any problem no difficulty would arise. As they cannot, special operating methods have to be used. The method on Atlas 1 is to have a special program called the Supervisor which controls the flow of programs through the computer. The Supervisor is simply a program which attempts to run Atlas in an efficient way, that is, it tries to keep all the parts of Atlas busy. To achieve this, it shares computing time between programs, and manages all peripheral transfers, including input and output as well as drum and magnetic tape transfers. The Supervisor is described in more detail later; at this stage it must be remarked that although it is not part of the hardware in the sense that the core store is, it is the most important single feature of Atlas and quite indispensable.
2.1.4 The main store on Atlas 1 consists of core store in units of 8192 words and magnetic drum store in units of 24,576 words. A total of about one million words are directly addressable. Up to 32 magnetic tapes can also be used as a backing store. The main store can consist of core store and drums in any proportion. The programmer treats the store as if it were all core store; he will in fact not know what parts of his program are in the core store at anyone time. The Supervisor manages drum transfers behind the scenes as required, and attempts to keep the most used blocks of program always in the core store, by means of a drum learning" program. This idea of a fast and a slow store appearing as a single fast store is called the one-level-store concept.
The Supervisor occupies most of a special store called the fixed store and some blocks of the main store. The fixed store is a read only store in multiples of 4096 words where binary ones and zeros are represented by ferrite and copper slugs in a wire mesh. It is used to represent permanent programs which will not be changed, and besides the Supervisor it holds the extra-codes. These are extensions to the basic instructions, described later. For working space the Supervisor has a subsidiary core store of 1024 words, which it keeps parameters associated with programs in the machine, peripherals, etc. The Supervisor also uses three magnetic tape units, called system tapes as part of its input/output organisation. All the stores used by the Supervisor are known as private store, and it is not possible for ordinary programs to interfere with them.
2.1.5 A large variety of input and output devices are allowed on Atlas 1. Each type of device is connected to the central computer via the peripheral co-ordinator, which contains buffer registers and information registers concerned with the transfer of data. These registers, which are at different places in the computer, and also some registers connected with the arithmetic units, are collectively referred to as the V-store. They are only accessible to the Supervisor, and form part of the private store. The peripheral co-ordinator allows the following types of input/output equipments to be attached.
| ICT TR5 paper tape readers | 300 ch/sec |
| ICT TR7 paper tape readers | 1000 ch/sec |
| Teletype paper tape punches | 110 ch/sec |
| Creed 3000 paper tape punches | 300 ch/sec |
| Creed 75 teleprinters | 10 ch/sec |
| ICT card readers | 600 cards/min |
| ICT 582 card punohes | 100 cards/min |
| Anelex line printers | 1000 lines/min |
| Graphical outputs | |
| Clock |
The following diagram shows the component parts of Atlas 1:-
Within the programmers store, registers are numbered consecutively from 0 upwards. Registers are arranged in blocks of 512 words called pages, and transfers between the core store and drums or magnetic tape take place in units of 512-word blocks. To increase the computing speed, the core store is divided into stacks, each with its own read/write circuitry. These are known as the even and odd stacks. Each is of 4096 words and they are arranged so that words 0, 2, 4, 6 .... are in the even stack, words 1, 3, 5 .... in the odd. Instructions are always called for by the control unit in pairs consisting of an even and the next odd instruction, although sometimes only one of these instructions may be wanted.
Whenever it is safe to do so, as soon as the control unit has decoded the odd address instruction it sends for the next pair. Thus, there is overlap between the execution of instructions and it is in fact possible for the computer to be in different stages of execution of up to five instructions. As a consequence, the first instruction in a pair must not alter the second and the second must not alter either of the next pair of instructions. Almost always, if this were done, the unaltered versions would be obeyed, but because of interrupts which occur at frequent intervals and which effectively insert instructions between program instructions sometimes the altered versions would be obeyed.
An Atlas 1 register, or word, contains 48 binary digits. These are conventionally numbered from 0 (most-significant) to 47 (least-significant).
A single word can be used to represent any of the following:-
Throughout this manual the binary digits of a word are numbered from the most-significant end, starting with bit 0. The engineers' numbering system is the reverse of this, and is used in some documents describing basic programs such as the Supervisor and Engineers' programs: in these documents bit 0 is the least-significant bit.
N can be taken as an operand directly in some instructions, in which case it is known as n. When N is used as an address, bits 1-20 specify a word in the main store, bit 21 specifies a half-word address and bits 22 and 23 specify a character address within a half-word (for the moment re-numbering the bits of N as 0-23). Instructions ignore irrelevant digits in the address. Thus an instruction involving half-words ignores digits 22 and 23 in the address. Digits 12-20 specify the word address within a block, and digits 1-11 specify the block.
Thus a main store address consists of
For the moment we shall write N as a decimal number and an octal fraction, separated by a point. Then 16.0 is the first half-word in word 16 (i.e. digits 0-23) and 16.4 is the less-significant half-word (digits 24-47), in an instruction which uses a half-word. In instructions for handling characters, the characters in word 16 are 16.0, 16.1, 16.2, .... 16.7; where 16.0 is digits 0-5, 16.1 is 6-11 etc., with 16.7 being 42-47.
The 10-bit function F is written as a single binary digit (f0) followed by three octal digits. For all basic functions f0 is zero, and may be omitted in the written form. The basic functions fall into three categories, depending on the first octal digit (f1 to f3); if this digit is 1, the function is a B-register instruction (B-code), if it is 2 the function is a Test instruction, and if it is 3, the function is an Accumulator instruction (A-code). These instructions are described in detail in later chapters.
The basic order-code is extended by the provision of extracodes. These are routines, written in basic instructions, which are positioned in the fixed store and which carry out many operations usually managed by a subroutine library. Extracodes are recognised by having f0 = 1. When this is encountered, main control is halted and the program continues under a special extracode control at an address in the fixed store. The final instruction in this routine (which is recognised by f1 = f3= 1 and obeyed as if f1 = 0) has the effect of returning to main control at the program's next instruction. Thus extracodes are subroutines with automatic entry and exit; to the programmer they appear as one instruction.
For example,
| Function | Meaning |
| 113 | is a B-code used to store a B-register |
| 234 | is a test-code, transferring n to Ba if the contents of the accumulator are zero |
| 374 | is an A-code, dividing the accumulator by the contents of a store address |
| 1250 | is an extracode, to unpack a 6-bit character from store and place it in Ba. |
The B-registers are used in different ways depending on the type of instruction. There are 128 B-registers, BO to B127, most of them of 24 bits. B120-127 are special purpose B-registers, the rest are general purpose. In A-codes, the contents of Ba and the contents of Bm are added to N to give a modified address. That is, the address S used in the instruction is N+ba+bm. In most B-codes, ba is used as an operand, so only bm is used to modify N, and then S = N+bm. (There are two exceptions, in which Bm is also an operand, so no modification takes place.) For most test codes, Bm is used as a further operand; where it is not it is used to modify N. In extracode instructions, Ba and Bm are treated in a special way. For the present we shall write Ba and Bm as decimal numbers in the range 0 to 127. B-register arithmetic is described in Chapter 4.
Instructions are written on one line, with the component parts separated:
F Ba Bm S
113 1 0 16.4 stores b1 in the half word at address
16.4 (B0 is always zero)
If b2 = 1.4 say, then
113 1 2 16.4 stores b1 at 18.0
If b1 = 3.0 say, then with b2 = 1.4,
374 1 2 16.4 divides the accumulator by the number at 21.0
Instructions are read into Atlas through the media of punched paper tape, either of 5-track or 7-track width, and 80-column punched cards. 7-track paper tape (the most common input medium) is prepared on a Flexowriter, 5-track paper tape on a Creed teleprinter and cards on a card punch. These three equipments have slightly different sets of characters. In the punched form, the parts of an instruction are punched as written and separated by multiple spaces or commas. Multiple space is two or more spaces on the teleprinter, or a tabulate (TAB) on the Flexowriter.
As explained in 2.4, address bits 1 to 11 represent the number of 512 word main store block to which that address refers, so that an Atlas 1 main store address refers to one of 2048 blocks. In octal (for the J notation see 4.3) these block addresses are JOOOO, J0001, JOO02,...., J3777 and in their decimal representation (see 5.6) 0:, 1:, 2:,..., 2047:. The ABL compiler and the program it is compiling share the same range of block numbers, with ABL occupying blocks in the range J3 to J34. Consequently to avoid over-writing itself ABL will refuse to compile program into any of the 256 blocks 1536: to 1791: Once the program is compiled and ABL has withdrawn from the store these blocks become available again and can be used as working space by the program.
The remainder of the main store block numbers J34 to J4 are illegal. ABL will not store program in block J3 or above and the Supervisor will fault the program if the compiled program attempts to refer to block J34 or above.
In fixed store and private store addresses bit 0 is a 1. There are therefore another 2048 blocks that can be addressed and they have octal addresses J4000 to J7777. The first 16 of these (J4 to J4017) are the block numbers of the fixed store and may be referred to by the programmer if he wishes, although there is generally no reason why he should do so. The block numbers J4020 to J4777 are also quite legal. In effect these block numbers refer to 31 consecutively stored copies of the fixed store. For example either of the instructions
101 3 0 J4017777
101 3 0 -1J5
would place the same half-word in B3, namely the left half of the last word of the fixed store. In other words addresses in the range J4 to J5 are in effect masked with J40177777 before execution (for a definition of masking, or what is the same thing collating, see 4.3)
The private store block addresses J5 through J7777 are completely forbidden to the ordinary programmer. These addresses can be referred to on extracode control. However it is impossible for the programmer to force an extracode to refer to the private store. He is prevented by faulting an extracode instruction in which the modified address is in the private store but the unmodified address is not. Thus for example a program containing the instruction
1730 0 0 J6 am' = sin(J6)
would be thrown off because the first instruction of the extracode routine is
324 0 119 0 am' = (b119)
(B119 will contain the address J6 upon entry to the extracode. See 7.2.)