This report on the PDP11/60 from Which Computer gives a good overview of the PDP11 Series at the time. The Plain Man's Guide from RAL gives some more information.
THE world's best-selling minicomputer family is based on a series of processors supported by common peripherals and more or less common systems software. All processors have the same basic architecture, with a similar input/output system and instruction set.
Technological advances, though, have led to some differences in development, and clearly a processor optimised for minimal low-end functions will not perform at peak efficiency in large multi-user, real-time systems.
As a result, there are three discernible lines of development within the PDP-11 family, distinguished by how they utilise the UNIBUS. Digital Equipment did not invent the idea of a single standardised data bus connecting all system components but it certainly popularised the idea.
The UNIBUS is asynchronous, connecting new system components - peripherals, processor, memory boards; it is simple and as a result newer and faster components can be added easily to replace older and slower devices. As a way of moving around data within a computer system, the UNIBUS is almost device independent.
One of the PDP-11 genealogical lines involves the 11/04 and 11/34. They utilise the standard UNIBUS; the larger, faster and more expensive 11/34 can transfer data at a faster rate but the principle is the same.
The LSI-11 and its boxed version, the 11/03, occupy a branch of their own. They do not have the UNIBUS per se, instead utilising a non-compatible bus structure called officially the sub-UNIBUS but referred to frequently as the Q-BUS. This retains the single-bus concept, though, and many of the standard PDP-11 peripherals can attach directly to it.
The other line of development began with the PDP11/45, promoted now only in its 11/55 incarnation, as a fast Fortran processor. This uses the UNIBUS but it also has a second high-speed data bus for fast transfers to and from memory. That highlights the problem with the single-bus approach - there is a limit on the aggregate throughput.
Because of the physical properties of the cabling and the electronics, there is an upper limit on the rate at which you can only push data along it. Attaching a number of system components and plenty of peripherals, all running resource-hungry applications, means that the UNIBUS can become clogged-up, and the system designers cannot alleviate the bottleneck by speeding the transfer rate. The second 11/55 bus, called the FASTBUS, takes some of the load from the UNIBUS. This approach was also adopted by the 11/70. The PDP-11/60, however, is in the 11/04-11/34 line. It utilises the UNIBUS alone and runs it at 2Mbps. The 11/60 fits between the 11/34 and 11/70, It uses the current range of technology in a mix which gives high computational power at a fairly competitive price. Since its introduction in Spring, 1977 sales in the U.K. have topped the 40 mark and worldwide the total is more than 600.
The machine is orientated towards high-performance, real-time applications and medium-performance, multi-user, multi-task, time-shared applications. The PDP-11/60 is offered in a variety of configurations. Every 11/6o uses the same basic CPU but models differ in the cabinet shapes and sizes, the range of peripherals supplied, and the amount and type of memory included in the basic packages.
A bootstrap loader and a display console are provided to facilitate operator control. Also standard is a 2KB cache memory facility, hardware multiply and divide, and 32- and 64-bit single- and double-precision floating point arithmetic. A faster floating point is provided as an extra-cost option.
Microprogramming is available to the more sophisticated user who is willing to master the internal structure of the PDP11/60 and write microcode for specific applications.
The design and packaging of the PDP-11/60 has placed great emphasis on the Reliability and Maintainability Program (RAMP). Digital Equipment seems to have put much effort into minimising down-time. This involves trying to cut back on MTBF - the cabinet has built-in cable runs and facilities, for instance. More impressive is the attention given to MTTR; there is continuous error-monitoring, several levels of diagnostics, fault isolation, in most cases to the board level, and easy module replacement.
You buy an 11/60 with at least 64KB and you can have it as a packaged system with two disc drives built in (2.5MB fixed plus 5MB cartridge; or two 14MB packs).
The processor utilises eight general-purpose registers; stack processing is, of course, standard; up to eight priority levels can be assigned and interrupts are handled automatically by a neat mechanism.
Physically the processor consists of six logic modules - in fact, they are printed circuit boards. The optional floating point processor uses four more slots in the backplane, the microcode extension option occupies one, and a serial line interface for the console always takes another.
A variety of configurations is available; all include this basic processor cage. Also on a .separate backplane are disc and peripheral controllers. Memory is on a third, backplane (the 11/66 uses 64KB cards) and a minimum of 64KB (one card) is always configured. The maximum of 248KB can be contained with the basic chassis but it is a fairly bulky unit in all its manifestations, at least by comparison with the 11/34.
The basic cabinet stands 125cm high by 120cm wide and 79cm deep. The 11/66 is sold usually in three versions:
The memory for the 11/60 consists of a 2,048-byte bipolar cache located within the processor, and either core or MOS memory in any combination of 64KB increments up to 256KB.
Parity is standard core; ECC (error correcting code) is optional on the semi-conductor memory. The ECC will detect and correct all single-bit errors before passing-on data accessed to the computer. As with most similar schemes, it cannot correct errors involving two or more bits; it does, however, detect and log multiple-bit errors. ECC is thus rather superior to the parity checking, which does no more than detect single-bit errors. MOS memory with ECC is approximately 60 percent more expensive on the 11/60 than core with parity checking.
The cache memory acts as a buffer between the central processor registers and main memory. Whenever a request is made to fetch data from memory, a check is made to see if the data is already in cache. If it is, no main memory read is required, the UNIBUS is not accessed and the instruction proceeds at the fastest rate.
If the data is not in cache, two bytes are transferred from main memory for execution. Benchmark tests - by Digital Equipment - have been done for what the supplier describes as an average program; information needed by the CPU is found in the cache memory 77 percent of the time. By comparison, other cache systems can have a higher hit rate - the 11/70 cache has the right information about 90 percent of the time.
As well as an increase in instruction execution speed, cache memory provides a lower UNIBUS utilisation by the processor; as a consequence, the UNIBUS is made available more often for transfers between I/O devices and memory. That overcomes the need for a dedicated, high-speed data channel and allows the 11/60 to perform well with the single bus.
Battery back-up is standard on the MOS memory. The rechargeable unit lasts 30 minutes if keeping power on to a full 256KB, two hours for 64KB.
Memory management in the PDP-11/60 is totally compatible with the memory management option on the 11/34 - and the older 11/35, and 11/40. This facility provides for memory extension, relocation and protection.
With the 11/60, Digital Equipment stepped boldly into user microprogramming. The 11/60 was not pioneering in this - several other middling-to-large systems could offer this method of implementing computer control. Microprogramming is considerably more detailed and much closer to the hardware than assembler programming.
Individual steps of data movement and manipulation can be controlled by the programmer. This allows increased flexibility, the ability to run faster and more efficient programs, and the opportunity to implement custom-tailored instruction sets. Microprograms relate closely to hardware operations, so decoding and executing them is very quick and they are held in fast-access memory, so getting them into execution mode is also speedy.
Three microprogramming options are offered to the PDP-11/60 user; note that only one of the options may be installed in the computer at the same time.
This is what other suppliers have termed Writable Control Store or WCS. It has all the software tools for program development. It provides 1,024 48-bit microwords of random-access memory. Each microword can be used either as one 48-bit-micro-instruction or as three 16-bit data words. By storing frequently-used data within the CPU in this fashion, the information can be retrieved at a cycle time of 170ns, the internal speed of the microcode processor.
The appeal of UCS will be strongest if you are an OEM buyer whose end-product makes the investment in microprogramming worthwhile. User-written microcode can be used to speed frequently-executed routines, so a commercial system might put data entry formats or mathematical calculations into UCS. A user could also give the machine new macro-instructions.
The ECS is hardware only. It comprises 1,536 48-bit words of read-only memory. It affords a means of permanent non-destructive storage for microprograms developed with the UCS option. ROM makes for very fast access, of course. To emphasise how much capacity ECS gives you, Digital Equipment is fond of pointing out that it could hold the entire PDP-11 instruction set.
This option contains 2K 48-bit words of ROM and represents a specific hardware-supported application of ECS. DCS is a fault isolator which facilitates fault identification in the central processor to the module level, usually an easily-replaced chip. Experience has shown that the DCS will locate something like 92 percent of all processor faults.
The 11/60 has more than 400 machine instructions. There is the basic PDP-11 set with some additions:
Digital Equipment apparently went to great lengths to produce in the PDP-11/60 a machine which is both reliable and easy to maintain:
We gather that field service engineers are delighted with the machine as they are rarely called out. This is corroborated by user experience; our poll of 11/60 installations showed a surprising degree of unanimity.
The 11/60 supports most of the main PDP-11 operating systems:
RSX-11M is the most commonly-used system on the 11/60s sold to date.
It was developed independently of RSX-11D and IAS, though each of these developments adopted the same user interface. RSX-11D was developed for the midrange PDP-11 processors (11/35 upwards), while the M version was aimed at a wider range (11/04 upwards). D was not suitable for the smaller machines because of its high memory requirement - which meant that memory management was needed - and because of its high processor requirement - the smaller PDP-11s were too slow in operation.
RSX-11M was launched in 1974 and in the intervening years has been subjected to two major upgrades, Version 3.0 being available since early 1977. An update to 3.1 has been available since early 1978.
RSX-11M can be configured to run on any PDP11 processor, with the exception of the LSI-11. It has a minimum requirement of 32KB and supports a maximum of 56KB if a memory management option is not available; in any. case the limit is 248KB on the 11/60.
It provides a resource-sharing environment, including the following features:
Facilities available to the user include an easy-to-use operator interface (MCR) which incorporates the ability to process predefined sets of MCR commands contained in files.
The File Control System (FCS) supports block-structured or record-structured files with full file protection and automatic space allocation.
Useful utilities include a text editor, the familiar PIP file manipulation facility, checks for file consistency, source file maintenance, and a crash dump analysis utility.
RSX-11M can be configured to be 2 single- or multi-user system. In its multi-user form it requires a minimum of 64KB, is able to handle up to 24 terminals, and incorporates a multi-user protection scheme.
Languages supported for the 11/60 are the MACRO-II assembler and Fortran II as standard. Fortran IV, Fortran IV-Plus and Basic are options. Other software available includes the DECnet networking facilities. RMS-11, a multi-key ISAM record management facility, can be used; the full DBMS-11 database manager is not supported. Both packages will be included in our review of minicomputer database systems.
One other rather curious item in the software catalogue is an application system for monitoring and control of power stations; it is not promoted heavily, to say the least.
RSX-11M acts as the host system for program development and system generation of RSX-11M systems. RSX-11S is a subset of M and is a memory-based system used for dedicated application environments. To operate it requires a minimum memory of 16KB; it is fully compatible internally with RSX-11M. Being memory-based, RSX11S does not support a file system, task check-pointing or dynamic memory allocation.
Machines up to 11/55 have the following configuration:
The UNIBUS allows addressing of any item hanging on it via a 16-bit field. This allows addressing up to 32K word. The first 28K of address space is core; the last 4K address disc, peripherals etc. All words are accessed in the same way; there is no distinction between i/o and memory. Thus MOV A,B can, for example, transfer data from any peripheral to core. The only exception is disc /memory transfers (DMA). This is done without CPU involvement (but see under Disadvantages). Any device on the UNIBUS can set itself up as the master by setting a flag; any other device can recognise the flag and become a slave.
Maximum 128K core. Maximum user segment 32K. A program's virtual address (16-bits) is mapped onto the real 18-bit address by one of eight registers (there are 2 sets of 8 registers - user and exec modes) - this applies to the 11/34 and 11/40:
One block = 32 words. The page address field maximum is 4K.
The 11/45 has two sets of 16 registers - allows 64K user space; separation of area into instruction and data sets and hence pure and impure code. Unfortunately this is not used by any DEC operating system; it is used by UNIX. Hence programs using more than 32K must be overlaid.
DEC have invented PLAS (Programmable Logical Address Space) to overcome this. This allows the user to move a 4K window over the core. It is not easy to use and there is no error protection. The operation is similar to dynamic equivalencing in FORTRAN or based variables in PL/1.
A recent DEC development is the FP11C - 4 times faster than the FP11B. It is only suitable for the 11/70; 11/55; 11/45 although the upgrade may be expensive if the 11/45 is old.
The standard protocol is the V24. The interface accepts serial input (eg from a teletype) and feeds 8 bits in parallel to the CPU on request. Available devices are:
Lineprinter, Magnetic tape, DECwriter, Tape reader, Tape punch, DEC tape decks, Card reader, Card punch, Tektronix, Teletype, Refresh display
