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Architecture of machines proposed for central Interactive Facility
C J Pavelin
ACD: Engineering Paper 36
This gives a brief summary of the architectures of 5 machines proposed for the interactive facility, followed by a table of comparisons. The machines are:
- BURROUGHS B6700
- CDC CYBER 173
- DEC KL10
- ICL 2980
- UNIVAC 1121
1. BURROUGHS B6700
The B6700 is designed as a multi-tasking Algol machine with special purpose registers and instructions implementing the stack, procedure call mechanism and other features necessary in a block-structured Algol-like language.
A program address space consists of a stack and other variable-size segments: program segments (which cannot be modified) and data segments. All data, other than that on the stack, is accessed through descriptors.
Processors and memory
Up to 3 identical central processors may initiate input/output on any of up to 3 I/O processors. All processors are connected to all memory modules (64K modules). Each I/O processor is capable of attaching to up to 20 peripheral units and to perform simultaneous operations on up to 10.
Registers and the stack
Every active job has an associated stack segment which contains variables, descriptors and control words. The latter enable the correct block structure to be maintained at procedure entry and exit.
The stacks of all jobs in the system form a cactus stack, a new branch being formed when one process begets another. The base stack of the structure contains the variables and descriptors of the operating system itself.
A set of registers known as the display (D0-D3l) points to the base of the sets of local variables (each set at most 512 words in length) within scope at each lexicographic level. These registers may point in any stack - thus D0 which is the outermost block of every process always points to the base stack, the others will normally point at the stack segment of the running process. The display is maintained by the instructions to enter and exit from procedures, using control words on the stack.
There are registers pointing to Base of Stack, current Top of Stack and Stack Limit. Two registers A and B (with extensions X and Y for double length operands) serve as the top-of-stack locations. Thus an operand in A may subsequently get pushed down into B and hence into the memory location pointed to by S.
Each stack. segment is identified by a stack number which indexes an array of descriptors for the stacks. This stack vector array is pointed to from a known location in the base stack (which is itself located from D0).
The word is 48 bits + 3 tag bits which are used to determine the format of the word. Thus the hardware can check, for example, whether a word is single precision floating point or a descriptor and that an operand is correctly used. Physical addresses are 20 bits. Some examples of word types are as follows.
|Single precision operand:||39 bit mantissa (an integer is a single precision operand with zero exponent)|
|Double precision operand:||(2 words, same tag on each) 78 bit mantissa|
|Data descriptor (DD):||20 bit address + 20 bit index or length|
|Program segment descriptor:||20 bit address + 20 bit length|
|Indirect reference word (RW):||5 bits identify display register + 9 bit displacement|
|Stuffed indirect reference word:||10 bit stack number + 16 bit displacement (identifies a block start in the stack) + 13 bit index|
|Program control word
Mark stack control word
Return control word
|procedure linkage control words kept on the stack|
Apart from variables within scope (ie within 512 words of a display register) on the stack, data and program code must be addressed through a descriptor. The basic three types are as follows:
- Data descriptor/segment descriptor:
- for accessing data or code in segments outside the stack
- Indirect reference word:
- indirect access of variables within scope
- Stuffed indirect reference word:
- access of stack variables outside scope.
All program segment descriptors are located in the base stack (operating system segments) or in the stack at level D1 and any procedure call must access (through one or a sequence of indirect reference words) a descriptor at one of these two levels. This means that operating system segments and complete user programs (but not individual user segments) can be shared.
Data descriptors can give an indefinite degree of indirection. There can be multiple copies pointing to the same segment (although all but one will have a copy bit set.
There is a presence bit in the descriptors so that an interrupt occurs when the segment is not in core. There is also a read only bit to prevent change to them in user mode.
Arrays can be further hardware segmented into fixed size pages of 256 words. There is a bit in the descriptor to indicate whether this segmentation has taken place.
Instructions (operators) consist of from 1 to 12 8-bit syllables. There are two processor states: normal and control, certain instructions being only legal in the latter state. Some typical instruction types are as follows.
- Wide variety of operations on top of stack entry or top two entries (A and B).
- Fetch or store B using address In A (DD or IRW).
- Value call - load in scope variable on top of stack (can apply indirection via DDs or IRWs).
- Name call - construct: an IRW at top-or-stack.
- Branch (conditionally on TOS entry) in current code segment.
- Procedure call to new segment, and procedure exit.
There are string operations, vector operations and an instruction to search a linked list.
2. CDC CYBER 173
The architecture is unusual in that there is a central processor (CPU) and 10 or more Peripheral Processors (PPU). The PPUs are identical programmable processors each with its own memory, and they are responsible for all I/O and control of the main CPU. Any PPU may use any I/O channel.
Main memory and registers
The word length in the CPU and main memory is 60 bits (ten 6-bit characters). Memory is in 4096 word banks, with full interleaving. There are eight 60-bit arithmetic (X-) registers, eight 18-bit index (B-) registers and eight 18-bit address (A-) registers. Integers (l's complement) are 60-bit, floating point operations give a 48-bit mantissa.
All addresses are 18 bits, giving a maximum of 256K user and physical address space. Addressing is datum/limit. A process is described by 16 memory words known as the exchange package area (part of a larger software structure - the control point) which contains datum limit, stored registers etc.
There are 15 and 30 bit instructions (may not overflow word boundaries)
15 bit instructions are typically: function, register, register
30 bit instructions are typically: function, register, 18-bit literal
or: conditional goto, 18-bit address
Fetches from, and writes to, memory are performed via the A-registers. Placing an address in one of the address registers A1-A5 causes the contents of that address to be loaded in the corresponding X-register (X1-X5). Similarly placing an address in A6, A7 causes a store from X6, X7.
Unusual instructions are:
- Population count: count of 1 bits in a word
- Exchange jump: swap processes to that described by a designated exchange package area (on earlier CDC machines this instruction only existed in the PPU).
There is a privileged processor mode - the monitor state although its only function appears to be to allow use of the exchange jump instruction.
The PPUs each have 4K words of 12 bit memory, with 12-bit addressing and one 18 bit accumulator. There are one and two word instructions with 6-bit function codes. The short instructions can only address the first 64 words of memory.
There are orders to read and write to central memory and any I/O channel, and to perform an exchange jump on the CPU.
3. DEC KL10
Processor and memory
KL10 may be single or dual processor. Control of all I/O is effected by the CPU over a single I/O bus. For slow devices all data is transferred over this. Fast devices controllers have direct connections to all memory modules over the memory bus.
There is a 36-bit word; user addresses are 18-bit (256K), physical addresses are 22 bit. Memory is in 128K modules with up to 4 way interleaving. The user sees 16 registers (addresses 0-15) which may be used for arithmetic or addressing. There are 8 blocks of these registers, one of which is assigned (by software) to a process.
There are 386 orders. Typical instruction format is: function, register, address. There can be single indexing of, and multiple indirection of, addresses. The whole 256K user space is directly addressable. There are single and double length floating operations (27 and 62 bits mantissa). Some unusual features are:
- instructions to allow byte addressing (any bit length of field within a word),
- manipulation of software stacks (for links etc)
- numerous half word operations,
- block moves of indefinite length.
There is single level paging. Pages are 512 words, the 9-bit user page number being mapped through a user page table onto a 13-bit physical page number. The page table entry contains Access Allowed, Write Allowed and public page (see below) bits. The whole page table is stored in a block of fast registers so the page number indexes this store. A page table in memory is contained in a larger 512 word table known as the process table.
There is a 2K cache, entries being made in 4-word chunks. Entries in the cache are tagged with physical addresses. There is no write-through to core when there is a write to the cache; core is only updated when necessary.
There arc two main processor modes: user mode (which disallows certain instructions) and exec mode. There is a separate process table for exec mode (defined by exec base register as distinct from user base register). However some part of exec address space is mapped using entries from the current user process table, and another part (first 112 pages) accesses physical memory directly.
There are two submodes of each mode. For exec there is supervisor mode and kernel mode. Only in the latter may the lower addresses be (physical memory) accessed and non-public pages changed.
User mode subdivides into public and concealed. In public mode, non-public pages may not be accessed other than to enter them at points containing a certain instruction. This entry itself effects the change to concealed mode.
4. ICL 2980
The 2980 is a virtual store machine with full paging and segmentation. It is stack based with special purpose registers implementing stack operations. Apart from segmentation, there is an additional protection mechanism which implements up to 16 different levels of privilege.
Processors and memory
There are one or more central processors (Order Code Processors) and one or more input/output processors (Store Access Controls). Each SAC is connected to up to 16 peripheral controllers.
Store is in blocks of 256K bytes (word length is 4 bytes = 32 bits). Up to 8 blocks of store form a unit, controlled by a Store Multiple Access Controller. The SMAC determines the access priorities to the unit of store with which it is associated. Each SMAC has four ports for connection to either CPU's or SAC's. Each SAC has 4 ports for connection to SMAC. There is also connection between OCP and SAC for I/O initiation and termination interrupts.
Instructions directly or indirectly refer to addresses of 32 bits which define byte positions in a virtual store of 232 8-bit bytes. The address space is segmented, with the top 14 bits of the address being the segment number. Segment numbers in the firs t half of the address space index a public segment table (shared by all processes), the others index the local segment table. Entries in the segment tables point to the physical segments or to page tables or to global segment tables giving a further degree of indirection (this is to facilitate sharing of local segments).
If a segment is paged, the page size is 1024 bytes (8-bit page number, 10-bit byte number).
There is an 8 entry associative register set: to contain recently accessed virtual/physical addresses.
Processor states and protection
A segment table entry has 24-bit keys - the Read Access Key and the Write Access Key - and an Execute Permission Bit. The processor runs in one of 16 levels, determined by the setting of an Access Control Register. A segment cannot read a segment if its RAK is less than the current ACR, similarly for writing and WAK. Apart .from interrupts, a process is only allowed to enter a more privileged ACR level through certain entries. The EPB must be set for execution of code. Together with the ACR level, there is a privileged state which enables access to certain state registers.
Registers and the stack
In the currently running process, one segment is designated as the stack - the segment number is contained in register SSN (Stack Segment Number). There is Stack Front Register pointing the first unallocated position in the stack, updated whenever items are stacked or unstacked.. A Local Name Base usually points to the local name space of the current procedure in the stack. An eXtra Name Base can address items at other stack levels.
There is only one arithmetic accumulator ACC, which can hold single, double or quadruple word operands.
There is also a 2-word description register DR (see below) and an index register B.
The order code consists of 16 or 32-bit instructions with the majority of operations being available in either form. Typical instructions load a register with an operand, optionally stacking previous contents. Direct operands are 7 or 18-bit literals or displacements relative to one of the address registers. Indirect access is achieved through a (possibly indexed) descriptor, on the stack or in the DR register. A descriptor is a 2-word pointer, the second word always being a full address. The other word contains information such as data type, scale factors as array bounds. Multiple indirection is possible. There is a range of store-to-store operations.
Analysis of instructions is pipelined (7 steps).
There are 3 slave stores; for instructions (256 bytes, 64 byte entries), stack operands (256 bytes, 16 byte entries) and off stack operands (512 bytes, 64 byte entries).
5. UNIVAC 1121
Processor and memory
The 1120 series may have one or two central processors. the CPU contains an I/O processing unit with up to 16 identical I/O channels. The word length is 36 bits with 18 bit user addresses.
There is a general register stack consisting of 2 sets of 64 words, 1 set for user mode (guard mode), one set for exec. Registers 0-15 of each set are index registers, 12-27 arithmetic accumulators (12-15 may be used for either). Other registers are for various special purposes or are not used.
Instructions are full word and have an operand address of 16 bits (thus 64K may be addressed directly). There is single indexing and multiple indirection. There are single and double length floating point operations (27 bit and 60 bit mantissa) and arithmetic on 1/6, 1/3, 1/2, single and double words.
The program can access two pairs of contiguous areas in its address space. Each pair consists of an Instruction (I-) and a Data (D-) Bank. The upper and lower bounds of each Bank in a pair are kept in the Storage Limits Register (SLR) and each address (instruction or data) is checked against the appropriate bounds. If the address is not in range, the limits of the other pair are loaded and a check made against them before giving an address error. (Since Bank address spaces can overlap, it is possible for an address to be interpreted as being in different Banks, according to what happens to be loaded in the SLR.) The limits for each pair of Banks are kept in the general register stack.
Any Bank may be write protected.
Mapping onto physical addresses is a simple relocation by adding on a base, one for each Bank. The bases for the current pair are kept in the Processor State Register. To enable up to 512K to be addressed (twice the 18 bit addressing range), there is an additional 1 bit kept somewhere. Banks may not cross the 256K boundary.
In exec mode, no check on the limits in the SLR is made. There is a privileged guard mode in which the SLR limits are checked only for writing.
There is a user mode order to replace Banks via a preset table of descriptors, that is without going to exec mode.
|Topic||CDC 173||UNIVAC 1120||DEC KL10||BURROUGHS B6700||ICL 2980|
|Word length (bits)||60||36||36||48+3||32|
|Addressable space: process||18 bits, 256K words||18 bits, 256K words||18 bits, 256K words||20 bits, 1Mword||32 bits (byte addressing)|
|Addressable space: physical||18 bits, 256K words||18 bits, 516K words
|22 bits, 4M words||20 bits, 1Mword||32 bits (byte addressing)|
|Memory mapping||datum/limit||quadruple data/limit
(2 instruction Banks, 2 data)
|paging (512 word pages)||segmentation; limited paging, 256 word pages||segmentation and paging, 1024 byte pages|
(full word unless otherwise specified)
8 index (18 bit)
8 address (18 bit)
|16 arithmetic/index||2 arithmetic (1 or 2 word)
32 display registers
stack control registers
|1 arithmetic ( up to 4 word)
2 stack address
1 index, 1 descriptor (2 word)
|Number of physical sets of registers||1||2 (exec and guard mode)||8 (assigned by software)||1||1|
|Processor states||normal, monitor||user, privileged user, guard||kernel, supervisor, public, concealed||normal, control||16 access control levels privileged, non-privileged|
|Protection (other than implied by memory mapping)||-||Banks, instruction or data. Any can be write protected||Access and write bits on page. Non-public pages protected in public mode.||Segments and descriptors can be write protected||Read and write access key on segment checked against access control level. Execute bit on segment|
|Length of orders||15 and 30 bit||36 bit||36 bit||8 bit - 96 bit||16 bit, 32 bit|
|Direct addressing range||256K (by loading address register)||64K + index||256K + index||stack within scope (512+Dn)||256K + namebase (byte address)|
|Indirect addressing type||-||multiple indirection (bit in address part)||multiple indirection (bit in address part)||descriptors, indirect reference words||descriptors (can be indexed)|
|Floating point mantissa (bits)||48||27, 60||27, 62||39, 78||24, 56, 112|
|Slaving etc||-||-||2K cache
512 word page table
|-||256 byte instruction
256 byte stack
512 byte operand
|Good features (comparatively)||10 PPUs for I/O and control||Large number of registers and powerful instruction set||Cache, register blocks, page table in registers, many processor states with rapid switching, powerful instruction set.||Powerful stack architecture, short instructions, vector instructions, tag bits indicate data type||Full segmentation, paging, large virtual store, good protection|
|Poor features (comparatively)||No virtual store, simple addressing||Addressing a mess, limited address space, long instructions, limited virtual store||Limited address space, long instructions, limited paging bits||Off-stack data access slow (descriptor must be fetched), no index registers||Considerable checking needed on calls to new ACR levels, limited no of registers|