Contact us Heritage collections Image license terms
HOME ACL ACD C&A Literature Technology
Further reading: □ OverviewPanels A, B and CPanel DPanel EPanel FPanel GPanel HPanel JPanel KPanel LPanel MPanel NAbbreviations
INF CCD CISD Harwell Archives Contact us Heritage archives Image license terms

Search

   
C&ATechnology195_Maintenance
C&ATechnology195_Maintenance
ACL ACD C&A INF CCD CISD Archives
Further reading

Overview
Panels A, B and C
Panel D
Panel E
Panel F
Panel G
Panel H
Panel J
Panel K
Panel L
Panel M
Panel N
Abbreviations

Panel E

Panel E: Floating/Fixed Point

This Panel, like Panel D, is concerned with the floating point and fixed point arithmetic.

It gives more specific information related to the three independent Adders and two Multiply/Divide (M/D) units. See Panel D for more information overall.

Each unit can run independently so there is a need for synchronising the activities so that the results appear correctly. Source and sink tags provide this.

The SHORT PRECISION indicator shows that the operation being accomplished is of that precision.

Registers are used to hold the data required for the arithmetic units. Once the unit has taken the data, it is able to mount its next data from the Common Data Bus (CDB).

To the bottom and left of the panel more indicators show the micro state of the multiply/divide unit that has a set of sub-cycle states as it performs either a multiply or divide.

The middle area contains additional information on the state of the units. The adder units have two stages and they can be processing two additions in the first and second cycle of the unit. Three reservation stations feed the adder units and two feed the multiply/divide units. Once the data has been consumed by the arithmetic unit the reservation station can start loading the next piece of data required in a subsequent operation.

The area to the right hand side is devoted to indicating the detailed state of the fixed point unit and its buffer registers.

See 360/195 Functional Characteristics for more detailed information.

BUSY FLIU M/D UNIT 1 L K SEL UNIT BUSY SRC REG FULL SNK REG FULL B0 B1 SOURCE TAG B2 B3 STOR OPND BIT B0 B1 SINK TAG B2 B3 SHORT PREC CDB REQ UNIT CDB ACPT MPLY OP DIV OP SRC UNN SNK UNN RO SR HI TO SHIFT RO SK HI TO SHIFT SRC FRAC ZERO SNK FRAC ZERO UNIT FIRST SK ON SHIFT BUS RO SINK HI B2 D4 EXEC FOR EXP 4 2 BAB 1 ADR BFRS 1 FULL SNB F-A TAGS FP AE FXP BRD CONTROLS 4 2 BAR A 1 BUSY FLIU M/D UNIT 2 M SEL UNIT BUSY SRC REG FULL SNK REG FULL B0 B1 SOURCE TAG B2 B3 STOR OPND BIT B0 B1 SINK TAG B2 B3 SHORT PREC CDB REQ UNIT CDB ACPT MPLY OP DIV OP SRC UNN SNK UNN RO SR HI TO SHIFT RO SK HI TO SHIFT SRC FRAC ZERO SNK FRAC ZERO UNIT FIRST SK ON SHIFT BUS RO SINK HI B2 D4 EXEC FOR EXP 4 2 BAB 2 1 FULL SNB F-B TAGS FP 2 BAR B 1 BUSY FLIU ADDER 1 N SEL UNIT BUSY SRC REG FULL SNK REG FULL B0 B1 SOURCE TAG B2 B3 STOR OPND BIT B0 B1 SINK TAG B2 B3 SHORT PREC CDB REQ FLIU CDB ACPT B4 B5 OP CODE B6 B7 START 1ST CYCLE 2ND RI RSLT INLK B1 SEL STK POS 1 B2 RI RSLT REG FLA UFLO RPT INH NOR RO 4 2 BAB 3 1 FULL SNB F-C TAGS FP AE 4 2 BAR C 1 BUSY FLIU ADDER 2 P SEL UNIT BUSY SRC REG FULL SNK REG FULL B0 B1 SOURCE TAG B2 B3 STOR OPND BIT B0 B1 SINK TAG B2 B3 SHORT PREC CDB REQ FLIU CDB ACPT B4 B5 OP CODE B6 B7 START 1ST CYCLE 2ND RI RSLT INLK B1 SEL STK POS 2 B2 STK CNTR B1 RO RSLT HALF FLA RSLT HALF M/D UFLO IRPT 4 2 BAB 4 1 FULL SNB F-D TAGS FP AE 4 2 BAR D 1 BUSY FLIU ADDER 3 Q SEL UNIT BUSY SRC REG FULL SNK REG FULL B0 B1 SOURCE TAG B2 B3 STOR OPND BIT B0 B1 SINK TAG B2 B3 SHORT PREC CDB REQ FLIU CDB ACPT B4 B5 OP CODE B6 B7 START 1ST CYCLE 2ND RI RSLT INLK B1 SEL STK POS 3 B2 STK CNTR B2 RO RSLT HALF FLA RSLT HALF M/D UFLO IRPT 4 2 BAB 5 1 FULL SNB F-E TAGS FP BAR C 4 BIT TRANSL BAR D 4 BIT BAR E 2 BIT BAR F 2 BIT SWITCH MPLY/ DIV R S 1 2 3 MULTIPLY/DIVIDE CYCLE COUNTER 4 5 6 MPLY PUL DVDR 1 2 3 MULTIPLY RING 4 5 STOP MPLY OSC FALSE START RESET LAST CYCLE SHORT DIV OP RSLT REG FULL MAIN ADDER CARRY OUT PROP ADDER PTY B0 M/D EXPONENT NORMAL SHIFT REGISTER B1 B2 B3 4 2 BAB 6 1 FULL SNB F-F TAGS FP 3 BIT 4 BIT SBO SNK ADR 5 BIT 7 8 9 10 11 12 13 DIV PUL DVDR 1 2 3 4 5 DIVIDE RING 6 7 8 9 START DIV OSC DIV END CYCLE FOUR UNIT RESET RO RSLT CDB LEFT 1 0 POST SHIFT RIGHT 1 UNIT 1 FIN UNIT 2 FIN ADJD PTY B9 EXP ADDER B8 1 2 3 FLP BFR REQ 4 5 6 SNK 2 SNK 1 FLP BFR CNCL FLOATING POINT FIXED POINT
⇑ Top of page
© Chilton Computing and UKRI Science and Technology Facilities Council webmaster@chilton-computing.org.uk
Our thanks to UKRI Science and Technology Facilities Council for hosting this site