The Storage Control Unit (SCU) controls the access of the central processing element (CPE)
to the high-speed buffer store and via that to the main store.
A CPE fetch from main store causes the requested address to be placed in one of three
Transfer Address Registers (TAR 1 to TAR 3).
A CPE output to main store causes the main store address of the transfer to be placed in on of three Store Address Registers
(SAR 1 to SAR 3). The state of the SAR and TAR Registers is indicated on the left hand side of the Panel.
Both sets of Registers need to know the current contents of the Buffer Store and this is provided by a Data Directory.
If the address fetched is already in the buffer store then the buffer store provides the contents.
If the address to be stored in is currently located in the buffer store then
this invalidates the current contents of the buffer store.
If the address requested is not in the buffer store, the double-word is transferred from main store to the CPE
and a copy placed in the buffer store. Frequently, store accesses are sequential so it also loads
the next seven double-words in the block to the buffer store to get ahead of future potential requests.
All eight double-words are placed in the same buffer storage segment.
While all this is going on, the channel requests to main storage take priority to ensure against channel overrun.
The Store Data Buffer (SDB1 to SDB3) contains the output to main store waiting to be delivered by the channel.
The aim always is to keep the last used 512 blocks of storage in the buffer store.
The 14 Channels available on the 360/195 are numbered 0-13.
The Storage Protection Facility (SPF) attempts to stop any Protection Violation (PV).
