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Further reading: □ Overview □ Panels A, B and C □ Panel D □ Panel E □ Panel F □ Panel G □ Panel H □ Panel J □ Panel K □ Panel L □ Panel M □ Panel N □ Abbreviations
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⟶ C&A ⟶ Technology ⟶ 195_Maintenance
⟶ C&A ⟶ Technology ⟶ 195_Maintenance
ACL ACD C&A INF CCD CISD Archives
Further reading ⇓

□ Overview
□ Panels A, B and C
□ Panel D
□ Panel E
□ Panel F
□ Panel G
□ Panel H
□ Panel J
□ Panel K
□ Panel L
□ Panel M
□ Panel N
□ Abbreviations

Panel F

Panel F: FIXED POINT / VARIABLE FIELD LENGTH / DECIMAL EXECUTION ELEMENT

This unit executes all fixed point arithmetic (FXP), logical, variable-field-length (VFL), and decimal arithmetic operations.

It consists of six major logical elements:

The state of the FXOS operation stack is indicated top left. Some operations are tagged as CONDITIONAL OP which means they are not decoded or executed until they are activated or cancelled by the instruction processor.

The IN PROCESS indicators show the type of instruction being processed (FXP, VFL, FXA). The execution of one operation can be overlapped with the decoding of the next.

See 360/195 Functional Characteristics for more detailed information.

FIXED POINT 1 2 3 FULL FXOS REGISTERS 4 5 6 1 FXA CTRLS CYCLE 2 3 PRI 0-1 2-3 4-5 6-7 8-9 GR SINK ADDRESS 10-11 12-13 14-15 ODD BYTE DBL RUA RESP 1 2 3 CONDITIONAL OP 4 5 6 FXP VFL IN PROCESS FXA GR ACPT 4 2 BUFFER 1 NAME 2 SAR 1 32 16 8 ITERATION COUNTER 4 2 1 RUM RESP 1 2 3 SET CC 4 5 6 FXP INSN OVLP VFL INSN OVLP FXOS DECR I GATE 8 COMPL 8 TRUE 4 COMPL 4 TRUE 4-8 ZERO MULTIPLE DECODE 2 COMPL 2 TRUE 1 BCOMPL 1 TRUE 1-2 ZERO 1 2 3 READ OUT 4 5 6 BLOCK OP SPC GR-A BFR-A BLOCK GR-B TO A ACC-R TO B ACC-L ADDER TO ACC-R FIXED-POINT DATA GATES SH TO ACC-R L-1 SHIFT R-4 SH STG-O SH TO GR A-B TO SDB BY TO SDB DATA AVAIL BEGUN ABORT HALF WORD CHECK GEN IG GR OP RESET A BUS NEG B BUS NEG NEG CARO ADDER OFLO FXP CC DATA A OUT ZERO NEG SHIFT OFLO S OUT ZERO COMPL NEG COMPL IF FB POS FB NEG CVB DIV CVD MPLY SHIFT FXP INSTRUCTIONS TIMER LM AND EX OR ADD GRP-1 OFLO GRP-1 A/S ALOGL-1 CONDITION CODE CONTROLS CMPR ATH-1 CMPR LOGL-1 DCML 1 START START EXEC SET OG BYTE EXECUTION CONTROLS BLOCK ONE P TGR OPND OVLP CVB DLYD FXB DVR 1 SKIP LIM 2 LEFT TIMER OG TO SDB LM PROC 2 CNTR PROCESS 1 FXP AND ADD GRP-2 OFLO GRP-2 A/S LOGL-2 CMPR ATH-2 CMPR LOGL-2 DCML 2 MVC SER S TIGR BLOCK STEP BYTE BUS VAL TSLT OVLP PROC T OFF OVLP TAGS CVB SIGN NEG COND OFLO 3 SKIP LIM 4 LOGL LM END LM END FTH LM MAKE REQ FETCH FC-FD FXP EX OR FXP SET CC VFL SET CC SHIFT SET CC ADD/ VFL 2 BYTE CC DATA 1 HOD LOD RSLT NON- ZERO STO TERM CPLT SIGN SAVE NEG CVD FIXUP CVD OG TO SDB FXP DIV DATA TIMER FTH PROT FXA IRPTS ADR EXCPN DCML DATA DCML DIV LAST OP VFL END SI END OP OP CPLT RDD SMP OG FILL DATA AVAIL FA CTRL REQ OUTST WRAP ARND REQ USED SINK CONTROLS NOTIF END WRAP ARND REQ USED SOURCECONTROLS NOTIF END SNK SRC IMM DATA OUTGATES SDB SS AP CP DP BYTE INSTRUCTIONS MP SP ZAP DATA AVAIL REQ OUTST START REQ FC NEXT FC CONTROLS REQ USE FC MALS END 0 1 2 3 WRTE DIRECT REGISTER 4 5 6 7 NC OC XC MVC MVN DATA AVAIL REQ OUTST START REQ FD NEXT FD CONTROLS REQ USE FD MALS END P 0 1 2 3 FILL REGISTER 4 5 6 7 MVZ CLC PK UNPK MVO 8 4 L1 COUNTER 2 1 8 4 L2 COUNTER 2 1 P 0 1 2 3 IMMEDIATE DATA REGISTER 4 5 6 7 ED EDMK TR TRT CLI 128 64 32 16 BYTE COUNTER 8 4 2 1 4 2 TW COUNTER 1 0-4 1-5 SKEW REGISTER 2-6 3-7 NI/OI/ XI TEST & SET TM WRD IC/ ISK FIXED POINT

BYTE INSTRUCTIONS Sub-panel

Indicates which instruction(s) being executed.

Name Description
AP Add Decimal
CP Compare Decimal
DP Divide Decimal
MP Multiply Decimal
SP Subtract Decimal
ZAP Zero and Add
NC And
OC Or
XC Exclusive OR
MVC Move
MVN Move Numeric
MVZ Move Zones
CLC Compare Logical
PK Pack
UNPK Unpack
MVO Move with Offset
ED Edit
EDMK Edit and Mark
TR Translate
TRT Translate and Test
CLI
NI/OI/XI
TEST & SET
TM
WRD
IC/ISK
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