This is a list of some of the abbreviated headings above the indicators at the top of the 360/195 Console. Not all are understood; we would appreciate any other entries that people recognise. The table also includes other 360 abbreviations of interest.
| A/S | Add/Subtract |
| ACC | Accumulator |
| ACC-L | Accumulator Left |
| ACC-R | Accumulator Right |
| ACVT | Activity |
| ADD/SUB | Add/Subtract |
| ADDER CARO | Adder Carry Out |
| ADDER OFLO | Adder Overflow |
| ADJD PTY | Adjusted parity |
| ADR BUFFERS | Address buffers |
| ADR CHK | Address check |
| ADR OUT | Indicates that information on bus-out is an address |
| ADR BFRS | Address buffers |
| ALLOW CMPR | Allow comparisons |
| ALTN SIGN | Alternative Sign |
| AND EX OR | AND Exclusive OR |
| AP | Add Decimal Instruction |
| ASCII | As an alternative to EBCDIC |
| AVAILABLE | Unit or Channel available |
| AXR | Add Normalised Instruction |
| BAL, BALR | Branch and Link |
| BC UCNDL | Unconditional Branch |
| BCR | Branch On Condition Instruction: NOP until all previous operations have been completed |
| BCT | Branch on Count Instruction |
| BEAT ADR | Light On when Address Increment not in normal position |
| BEAT BSM | Light On when Address Increment not in normal position |
| BFR | Buffer |
| BLANK OR AST | Blank indicates correct parity, Asterisk indicates incorrect parity |
| BLK CLC | Block Compare Logical |
| BLOCK MPX CHAN MODE | Block Multiplex Channel Mode |
| BLOCK SCAN | Address Increment (Block Scan) |
| BLOK MODE | Block Mode |
| BR TAKEN | Branch taken |
| BSAB | Buffer Store Address Bus |
| BSM | Basic Storage Module. The 360/195 comes with a spare BSM |
| BTAM | Basic Telecommunications Access Method |
| BUS OUT | Bus-Out Check |
| BUSY | Unit or Channel busy |
| BXLE | Branch on Index Low or Equal |
| CANCEL GR REQ | Cancel General Register Request |
| CANCEL MS | Cancel Main Storage Request |
| CAR | Console Address Register: 24 address switches and three parity switches used to set an address in the CAR (Panel M) |
| CARO | Carry Out (Adder) |
| CBR | Console Buffer Register |
| CBR TO ZEROS | Console Buffer Register all to 0 |
| CBR TO ONES | Console Buffer Register all to 1 |
| CC | Conditional Code or Channel Command |
| CCW | Channel Command Word |
| CC MASK | Conditional Code Mask |
| CC SYNC | CC Synchronous Idle |
| CDB | Common Data Bus |
| CDB ACPT | CDB Accepted |
| CDB REQ | Request to use CDB made by specific arithmetic unit |
| CDB TAG ADR | Tagging of the CDB to ensure proper sequencing of operations |
| CE | Customer Engineer |
| CDU | Coolant Distribution Unit |
| CHAN | Channel |
| CHAN INTF BUSY | Channel Interface Busy |
| CHAN SEL | Channel Selected |
| CHANNEL REQ IN PROCESS | Channel Request in Process |
| CHK | Check |
| CHRON | Chronology |
| CLC | Compare Logical |
| CMND | Command |
| CMND OUT | Indicates that information on bus-out is a command |
| CMPR ATH | Compare Arithmetic |
| CMPR LOGL | Compare Logical |
| CNCL | Cancel |
| CND CODE | Condition Code (PSW 34-35) |
| CNDL | Conditional |
| CNDL BACK < 8 | Conditional instruction less than 8 back so loop can fit in instruction buffer |
| CNDL MODE | Conditional Mode |
| CNTR | Control |
| COND | Conditional |
| CONDITION CODE CONTROLS | Condition Code in the PSW is set by most logical operations and is used by subsequent branch-on-condition operations |
| CONDITIONAL MODE | Alternative to LOOP MODE |
| CP | Compare Decimal |
| CPC HARD STOP | CPC Hard Stop Setting |
| CPE | Central Processing Element |
| CPLT | Complete |
| CPLTD | Completed |
| CPU | Central Processing Unit |
| CRT DISPLAY & TAPE OP | CRT Display and Tape Operation |
| CTRL | Control |
| CYCLE 1ST 2ND | Each floating point adder has 3 reservation stations and can can be executed concurrently once data is available by offsetting the start of one operation by a cycle. While two reservation stations are in action the third can be acquiring data |
| DATA AVAIL | Data Available |
| DATA DIRECTORY | Part of the Storage Control Unit (SCU) |
| DBL | Double |
| DCD | Decode |
| DCML DIV | Decimal Divide Program Exception, PSW 27 |
| DCML OFLO | Decimal Overflow Program Exception, PSW 26 |
| DEU | Decimal Execution Unit |
| DIV OP | Specific M/D Unit is executing a divide |
| DLY SAR MODE | Delay SAR Mode |
| DP | Divide Decimal Instruction |
| DPLY ADDR | Display Address |
| DSBL INTV TIMER | Disable Interval Timer |
| DW | Double Word |
| ED | Edit |
| EDIT | Edit Instruction |
| EDMK | Edit and Mark |
| EX OR | Exclusive OR |
| EXCP | Exception |
| EXCPN | Exception |
| EXP DIFF | Exponent Difference |
| EXP DIFF SUM | Exponent Difference |
| EXP OFLO, UFLO | Exponent Overflow, Underflow Program Exceptions, PSW22, PSW23 |
| EXP -14 | Shifts more than 14 get a 15 shift |
| EXT SGL | External Signal |
| FAU | Add execution unit |
| FD | Fetch Data |
| FD CONTROLS | Fetch Data Controls |
| FEU | Floating point Extended Execution Unit |
| FEU SHIFTER IN, OUT | Floating-point Execution Unit |
| FEU RESERVATION | State of Floating-point Execution Unit |
| FLB | Floating Point Operand Buffers 1, 2, 3, 4, 5, 6 |
| FLB TAG ADR | TAGs used for maintaining correct synchronisation |
| FLIU BUSY | Floating Point Instruction Unit Busy |
| FLIU SEL | Floating Point Instruction Unit Selected |
| FLOS | Floating Point Operation Stack 1-8 |
| FLP | Floating Point Registers |
| FLP DIV | Floating Point Divide |
| FLP M/D | Floating Point Multiply//Divide |
| FLP MULTIPLY/DIVIDE | Floating Point Multiply//Divide |
| FLP OPERATION STACK | Floating Point Operation Stack 1-8 |
| FLP REGISTERS | Floating Point Registers |
| FLR | Floating Point Registers 0 2 4 6 |
| FLR TAG ADR | FLR tags give information about the operation being performed |
| FLRB | FLR Bus |
| FMDU | Floating Point Multiply Divide Unit Execution Unit |
| FXOS CNTR | Fixed Point Operator Stack Control |
| FXB | 6 32-bit Fixed-Point Operand Buffers |
| FXB DVR | 6 32-bit Operand Buffers |
| FXEU | Fixed-point Execution Unit |
| FXOS | Fixed Point Operation Stack, 6 positions |
| FXP | Fixed Point arithmetic used to perform arithmetic operations on both data and storage addresses. Word is a 32-bit signed integer (high order sign bit) 16-bit working also |
| FXP AND | Fixed Point And Instruction |
| FXP & FLP OP STACK | Instructions in the Operation Stacks are decoded serially and issued to the appropriate unit. Overlapping takes place when possible |
| FXP & FLP STO BFR | The store buffers for both units contain operands waiting to be processed |
| FXP BFR | Fixed Point Operand Buffer |
| FXP CC DATA | Condition Code in the PSW is set by most logical operations and is used by subsequent branch-on-condition operations |
| FXP DIV | Imprecise Interrupt |
| FXP INSN OVLP | Fixed Point Instruction overlapped with decoding next instruction |
| FXP INSTRUCTIONS | Fixed Point Instructions |
| FXP OFLO | Fixed Point Overflow Program Exception, PSW 20 |
| GR | General Registers 0 to 15 for use of the Fixed-Point/VFL/Decimal Execution Element |
| GT | Gate |
| HALF WORD | 16-bit halfword |
| HI | High |
| HRD STP | Hard Stop |
| I/O | Input/Output |
| IGNR CPU CHKS | Ignore CPU checks |
| ILC | Instruction-Length Code |
| IPL | Initial Program Loading |
| I/O IRPT TAKEN | Input/Output |
| I/O VALID | Input/Output |
| IC | Instruction Counter |
| IGNR CPU CHKS | Ignore CPU Checks |
| ILGL OP CODE | Illegal Op Code |
| IMM | Immediate |
| INCR | Increment |
| INH ADR ACPT | Inhibit Address Accept |
| INH BFR | Inhibit Buffering |
| INH INSN FTH | Inhibit Instruction Fetch |
| INH OVLP | Inhibit Overlap |
| INHIBIT REPLACE BUFFER SEGMENT | Inhibit Replace SCU Buffer Segments |
| INHIBIT REPLACE SCU | Inhibit Replace SCU Buffer Segments |
| INIT FTH | Initialise Instruction Fetch |
| INPUT/OUTPUT CHAN | Input/Output Channel |
| INSN LENGTH | Instruction Length (PSW 32-33) |
| INSN FTH | Instruction Fetch |
| INSTRUCTION ADDRESS | (PSW 40-63) |
| INTV | Interval |
| INV PTY | Invert Parity |
| IO | Input/Output |
| IPL | Initial Program Load |
| IR | Instruction Register |
| IRC | Instruction Length Codes |
| IRPT | Interrupt |
| I/O IRPT TAKEN | I/O Interrupt taken |
| LAST CYCLE | Buffers are released during the last cycle |
| LB | Lower Bound Register, points to the earliest double word brought into stack |
| LM | Load Multiple |
| LO | Low |
| LOG | Some interrupts are logged rather than obeyed immediately |
| LOGL | Logical |
| LOG WD | Log Word Display |
| LOOP MODE | Instruction Processor can be in Loop Mode, alternative is Conditional Mode |
| LOST SGNF | Significance Program Exception |
| M/D | Multiply/Divide Unit |
| M/D EXPONENT | Multiply/Divide Exponent |
| M/D UFLO IRPT | Multiply/Divide Unit Underflow Interrupt |
| M/D OFLO IRPT | Multiply/Divide Unit Overflow Interrupt |
| MACH | Machine |
| MACH CHECK ENABLED | Machine Check Enabled |
| MACH CHECK STOP | Machine Check Stop |
| MACH CHK | Machine Check |
| MALS | Malfunctions |
| MAN | Manual |
| MCW | Machine Check |
| MP | Multiply Decimal Instruction |
| MPLY DCD | Multiply decoded |
| MPLY OP | Specific M/D Unit is executing a multiply |
| MPX | Multiplexor |
| MS | Main Storage |
| MULTIPLY/DIVIDE CYCLE COUNTER 1,12 | The floating point multiply/divide unit was implemented using a subcycle, which reduced 12 partial products each subcycle |
| MVC | Move |
| MVN | Move Numeric |
| MVO | Move with Offset |
| MVZ | Move Zones |
| MX NORM | MXR, MXDR, MXD Extended Precision Floating Point Instruction can deal with Normalized and Unnormalized numbers |
| MXD | Extended Precision Floating Point Instruction |
| MXDR | Extended Precision Floating Point Multiply Instruction |
| MXR | Extended Precision Floating Point Multiply Instruction |
| MXR M/D UNIT REQUEST | Request to use Multiply/Divide Execution Unit |
| NC | And |
| OC | Or |
| OFLO | Overflow Program Exception sets PSW bit |
| OP CODE B4 to B7 | Op Code used in Adder Unit |
| PCI | Program-Controlled Interrupt |
| PDU | Power Distribution Unit |
| PK | Pack |
| POST NORM | Post Normalisation in Floating Point Adder (D) |
| POST SHIFT DCD | After Shift in Floating Point Adder (D) |
| PPLN NOT EMPTY | Pipeline Not Empty |
| PRGM CHECK RESET | Resets Storage and error checks |
| PRIV | Privileged |
| PROT KEY | Protection Key, bits 8-11 of PSW |
| PROT VIOL | Protection Violation |
| PROTECT KEY | Protection Key, bits 8-11 of PSW |
| PSW | Program Status Word |
| PTY | Parity |
| PTY CHK | Parity Check |
| P V | Protection Violation |
| Q | Queue, Storage Protection Key in PSW |
| RATE | Rate Setting (Rotary Switch) |
| REG | Register |
| REGS | Registers |
| REL | Relative |
| REPLMT CODE | Replacement code, keeps order of buffer store use |
| REQD TRSFR | Required Transfer |
| RESRVN STATION GATE | Reservation Station Gate, stations sit in front of add and multiply/divide uexecution units |
| REV MARK PTY | Reverse mark parity |
| REVERSE CBR PTYS | Reverse CBR Parities |
| RPT | Repeat |
| RSLT NON-ZERO | Result non-zero |
| SAR | Store Address Registers 1, 2, 3 |
| SAR COMPARE | Storage Address Register Compare stops CPU successful data address comparison |
| SBI PTY | Storage Bus In Parity |
| SBO | Storage Bus Out |
| SBO PTY | Storage Bus Out Parity |
| SC | System Console |
| SCU | Storage Control Unit. One of the 5 units (processor storage, fixed point/VFL/decimal Processor, floating point processor, instruction processor also) |
| SDB | Store Data Buffer for output to main store from a channel |
| SDK TAG B0 to B3 | Sequencing Tags for arithmetic unit output |
| SEL HOLD OUT | Selector Channel |
| SEL LEFT, RIGHT | Selector Channel |
| SET MODE CMND | SM: Set Mode Command |
| SET WD CNTR | Set Word Counter |
| SGNF | Significant |
| SHFTR FRAC | Shift Right Fraction Part |
| SHORT DIV OP | Short Precision |
| SHORT PREC | Short Precision indicated for a specific arithmetic unit |
| SINK TAG | Tags B0 to B3 controlling sequencing of output from specific arithmetic unit |
| SLI | Suppress Length Indication |
| SNK FRAC ZERO | Output from arithmetic unit has zero fraction |
| SNK RDY | Sink Ready |
| SNK REG FULL | Output from specific arithmetic unit is available |
| SNK UNN | Result for specific unit is unnormalised |
| SOFT STOP | CPU in stopped state when specific instruction address reached |
| SOURCE TAG | Tags B0 to B3 control sequencing of operations through the arithmetic units |
| SP | Subtract Decimal Instruction |
| SPF | Storage Protection Feature |
| SRC FRAC ZERO | Input to arithmetic unit has zero fraction |
| SRC REG FULL | Specific arithmetic unit has information ready in registers |
| SRC UNN | Specific Unit is dealing with unnormalised number |
| STACK CNTR | Stack Control |
| STEP BYTE CNTR | Step Byte Counter |
| STEP CMND CNTR | Step Command Counter |
| STEP WD CNTR | Step Word Counter |
| STEP WORD CNTR | Step Word Counter |
| STOP ON PTY CHK | Stop on parity check |
| STORAGE TEST | Start Storage Test |
| SVC | Supervisor Call |
| SXR | Subtract Normalised Instruction |
| TAR | Transfer Address Register |
| TAR FTH BFR | Transfer Address Register Fetch Buffer |
| TAR COMPARE | Comparing two Transfer address registers |
| TAR ON BSAB | TAR on Buffer Store Address Bus |
| TEMP FTH | Temporary Fetch Instruction |
| TIC | Transfer In Channel |
| TM | Test Under Mask Instruction |
| TMR CHK | Timer Check |
| TO BSAB GATE SC | To Buffer Store Address Bus from System Console |
| TO BSAB GATE TAR 1, 2, 3 | To Buffer Store Address Bus from Transfer Address Register |
| TO SAB | To Store Address Bus |
| TR | Translate Instruction |
| TRANSL | Translate |
| TRSFR | Transfer |
| TRT | Translate and Test |
| UB | Upper-bound register, points to most recent double word brought into stack |
| UFLO | Underflow |
| UNIT BUSY | FLIU Busy |
| UNIT CDB ACPT | Specific arithmetic unit given access to CDB |
| UNN | Unnormalised floating point number |
| UNPK | Unpack |
| VFL | Variable Field Length |
| VFLEU | VFL Execution Unit |
| VFL INSN OVLP | Variable Field Length instruction overlapped with decoding of next instruction |
| VFL PTY | VFL Parity |
| WAIT | CPU in WAIT State |
| WRAP ARND | Wrap Around |
| WRD | Write Direct |
| XC | Exclusive OR Instruction |
| ZAP | Zero and Add Instruction |
| ZERO DET | Zero Determinant |
