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C&ATechnology195_Maintenance
C&ATechnology195_Maintenance
ACL ACD C&A INF CCD CISD Archives
Further reading

Overview
Panels A, B and C
Panel D
Panel E
Panel F
Panel G
Panel H
Panel J
Panel K
Panel L
Panel M
Panel N
Abbreviations

Panel G

Panel G: Instruction Unit

Instructions are fetched from storage and stored in the instruction stack. Instructions fetched from storage are stored in the instruction stack of the instruction processor. This minimises storage access time and reduces the number of instruction fetches if executing a tight loop.

The stack contains the current instruction doubleword, and seven double words of instructions already decoded or instructions to be executed.

After decoding an instruction, it can be sent to one of three execution units (Instruction Processor, Fixed-Point/VFL/Decimal, Floating Point).

During decoding of an instruction, it needs to check that the execution unit is ready to accept the instruction, that the buffers for any operand needed are available.

It also may use its own adder to calculate an address.

Some instructions may depend on a branch instruction for execution so they need to be marked as unconditional (UCNDL) or conditional (CNDL). The execution units continue to function as though the instruction is to be executed but are marked as conditional.

For a store instruction, checks must be made that the address is not one in the stack.

The instruction stack can be placed in LOOP mode when the set of instructions in a loop all reside in the instruction stack.

Branch execution (BR-EXEC) will cause the target address to be added to the instruction stack.

See 360/195 Functional Characteristics for more detailed information.

INSTRUCTION UNIT INSN FTH INIT FTH TEMP FTH INSTRUCTION FETCH IMRT ISR PROT VAL OP OG OP REG SYLL 00 # B-D OG VAL OP OG OP REG SYLL 01 B-D OG INSTRUCTION PIPELINE CONTROL VAL OP OG OP REG SYLL 10 B-D OG VAL OP OG OP REG SYLL 11 B-D OG 4 2 FX OS CNTR 1 8 EXECUTION BUFFER STATUS 4 FL OS CNTR 2 1 4 2 STATE TGRS 1 BR-EXEC-MULTI CYCLE OP SEQUENCE SV R1 INVAL R1 DBL SNK GR REQ CANCEL GR REQ SIT SIAT NIAT 0 1 2 # 3 4 5 6 7 GR OG R1-B TO ADDER A INPUT 8 9 A B C D E F A B BUSY FXP BFR C 1 2 BUSY FLP BFR 3 LOOP MODE BC UCNDL BAL BXLE BCQ BXQ 0 1 FETCH TAGS 2 3 TEMP 1 0 1 2 # 3 4 5 6 7 GR OG R2-X-R3 TO ADDER B INPUT 8 9 A B C D E F D E F 4 5 6 TFM TF1 TF2 BR TAKEN BACK < 8 BIA BIA1 4 5 6 7 TEMP 2 WR TEMP TO A SVIR # LB T/C→C WR TEMP DWCR TO B BY BFR MISC GATING TO ADDER L1 L2 IR CTR TO D D BFR 25 28 HOT 1 TO ADDER 29 31 4 2 FXP BFR BUSY CNTR 1 1 2 SAR BUSY 3 CNDL MODE CC VAL ACVT CNCL EXEC A EXEC B EXECUTE EXEC C +2 TO IR CTR 0 1 2 PROTECT TAGS 3 TEMP 1 1 2 3 SINK ADR # 4 5 TEST & SET FTH STO PIPELINE 2 OPERATION C H LENGTH F D CNDL 2 1 SAR SET CC FXP VAL OP STAGE VAL FLP 0-7 PTY T1 T2 TIMER GO TAT 8 4 CC MASK 2 1 SAVE INH R1 OG 1 2 FETCH TAGS 4 5 6 7 TEMP 2 1 2 3 SINK ADR # 4 5 TEST & SET FTH STO PIPELINE 3 OPERATION C H LENGTH F D CNDL 2 1 SAR INH PROT SPF VFL TRSP SUP SMAL SCU NOT ACPT REQ 1ST REQ 2ND BOO PPNL 3 REQ DBL CNDL QUICK CNDL BACK < 8 CNDL BIA 1 2 PROTECT TAGS 1 2 INVALID TAGS
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