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C&ATechnology195_Maintenance
C&ATechnology195_Maintenance
ACL ACD C&A INF CCD CISD Archives
Further reading

Overview
Panels A, B and C
Panel D
Panel E
Panel F
Panel G
Panel H
Panel J
Panel K
Panel L
Panel M
Panel N
Abbreviations

Panel H

Panel H: Instruction Unit: Interrupt Control and Manual Control

The set of imprecise overflows DCML OFLO onwards at the top normally cause a change to the 8-byte PSW (Program Status Word) that is indicated here. Bits 16 to 31 indicate the type of interruption:

16 	STOR PROT   Protection
17 	ADR         Addressing
18 	SPEC        Specification (not used on 360/195)
19 	DATA        Data
20 	FXP OFLO    Fixed-Point Overflow
21 	FXP DIV     Fixed-Point Divide
22 	EXP OFLO    Exponent Overflow
23 	EXP UFLO    Exponent Underflow
24 	SGNF        Significance
25 	FLP DIV     Floating-Point Divide
26 	DCML OFLO   Decimal Overflow
27 	DCML DIV    Decimal Divide

An External interruption (EXTERNAL CAPTIVITY/IDENTITY) occurs as the result of certain asynchronous events:

TIMER    Timer
KEY      Interrupt Key
2-7      External Signal 2-7

Below the Interrupt Controls on the left are displayed the contents of the PSW.

0-7    System Mask              Bits 0 to 5 enable channels
                                Bit 6 for Channels 6-13
                                Bit 7 enables external interruptions (EXT SGL)
8-11   Protection Key           PROTECT KEY
12     ASCII mode               enable ASCII mode for packed decimal instructions
13     Machine checks           enable Machine check interruptions 
14     Wait State               processor is halted
15     Problem state            enable to prevent the use of instructions reserved for supervisor state 
16-31  Interruption Code        code to indicate the type of interruption
32-33  Instruction Length Code  INSN LENGTH length in halfwords or 0 if unavailable 
34-35  Condition Code           CND CODE
36-39  Program Mask             enables the four interrupts
40-63  Instruction Address

See 360/195 Functional Characteristics for more detailed information.

INSTRUCTION UNIT INTERRUPT CONTROL INT MACH CHK IRPT EXT DCML OFLO DCML DIV DATA FXP OFLO FXP DIV EXP OFLO EXP UFLO IMPRECISE SGNF FLP DIV STOR PROT SPEC A ADR A SPEC A CND ADR A CND OP SPEC B PRIV PRECISE EXEC ADR B MAN STT 2 SNG CY 1 MANUAL CONTROL I ADR CMPR HRD STP 1 2 MOP STATE 3 MOP SEQUENCE MOP L-REG FULL SPV CALL IRPT 2 IRPT SEQ 1 TIMER KEY 2 3 EXTERNAL CAPTIVITY 4 5 6 7 TIMER KEY 2 3 EXTERNAL IDENTITY 4 5 6 7 STOP STATE INSN STEP SNG I DCD FLP M/D SNG CY OPND ACCS SRC 1 MORE SNK MARK INH ADV TO WR TERM OPND OVLP PRGM B IRPT IRPT SEQ B IRPT F/S →F INH WR ADR PSW STD I/O IRPT TAKEN CH REL PPLN NOT EMPTY BYTE 1 BYTE 2 CRT-UB PTYS BYTE 3 MPX 8 4 INPUT/OUTPUT CHAN 2 1 MISC MAN STOP OVLP STOP DCD FLP M/D SNG CY RATE BYTE BFR VAL REQ PAT OR ARG LAST REQ EDIT SRC BLK CLC LLO3 OG R1 TO R1 OR OG 0-7 P PSW 0 MPX CH 0 1 2 3 SYSTEM MASK SELECTOR CHANNEL 4 5 6-13 7 EXT SGL 8-15 P 8 9 PROTECT KEY 10 11 ASCII MACH CHECK ENBLD WAIT PROB STATE 32 INSN LENGTH 33 34 CND CODE 35 FXP OFLO DCML OFLO PROGRAM MASK EXP UFLO LOST SGNF 8 9 10 11 12 13 14 15 16 17 18 19 INSTRUCTION ADDRESS (PSW 40-63) 20 21 22 23 24 25 26 27 28 29 30 31 0-7 P CXR INH OVLP SWITCH BITS STO ADDR INV & SWITCH DLY SAR MODE DSBL INTV TIMER INH ADR EXCP CHAN REL 2 MCW COUNT ACTION 8-15 P 1 PRGM CHECK RESET IGNR CPU CHKS INH RST ADR SIM WRAP CHAN DIAG CODE DATA REV MARK PTY ADR P & KEY CHKS 16-23 P SINK ADR INV PTY OP STAGE FXP ADDER CHK GEN I-BOX ADDER 1 2 INHIBIT REPLACE BUFFER SEGMENT 3 4 24-31 P INH INSN FTH SAR TAR SEL FP M/D PULSE STOP 27 28 SAR 29 FLP CHK-GEN (BITS 27-32) 30 TAR 31 32-39 P C-G 32 8 ON=FLP 4 CHAN ID 2 4 FXP & FLP OP STACK 2 1 CODE 1 25 4 26 BSM ADR 2 27 CODE FXP & FLP STO BFR 1 28 40-47 P S/F LD & START 2 LD & STOP SRC CODE FLP SNK/ 1 OFF LINE 44 QW REQ 45 46 USE WHEN MCW TO CHAN SIM SW IS ON 47 CHECK GENERATE BITS 48-55 P 48 49 50 51 52 2048 53 1024 54 512 55 256 56-63 P 56 128 MCW COUNT FIELD 57 64 32 58 59 16 60 8 61 4 62 2 63 1
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