The Floating Point Processor on the 360/195 was similar to this description of the 360/91 Processor but
with a number of differences. The descriptions below give some idea what the various displays in Panel D indicate via the cryptic headings.
The left hand side of Panel D is concerned with floating point addition and subtraction. The floating point format had a
single-bit sign bit followed by a 7-bit characteristic
or exponent. The remaining bits defined a normalised version of the fractional part SHORT: 24 bits.
Performing an addition requires:
Comparing the characteristics to align the fractions before attempting the addition/subtraction
Performing the addition and/or the subtraction. Subtraction just required complementing the bits of the fraction before the add operation.
Re-normalising the result
A special case is where the characteristics are different by 14 or more in which case they are treated as though the difference was 15
which results in the smaller number becoming zero. (EXP 14 light indicates when this occurs).
The floating point execution unit has an operation stack (FLOS) of 8 positions, four separate registers (FLP REG 0,2,4,6)
supported by six operand buffers registers (FLB 1-6) and details about their current contents
are indicated by the bottom left section of displays. The add unit has three reservation stations.
Several operations can be in various stages of execution at the same time so a system of TAGging of the common data bus (CDB) ensures
proper sequencing.
An extended precision floating point number has a 28-bit fraction and consists of two long-precision floating point numbers,
called the high-order (HI) and low-order (LO) bits. Extended precision operations are AXR (add), SXR (subtract), MXR (multiply)
and MXD/MXDR (extended multiply)
Decimal arithmetic is also included in the order code primarily aimed at commercial applications
using 4 bits per decimal digit.
