Words, words, mere words,
no matter from the heart.
(Troilus and Cressida. V.iii. 109)
Control Data takes great pleasure in presenting this proposal to the Atlas Computer Laboratory, Science Research Council, for the purchase of a high performance computer system.
Section 1 of this document summarises the proposal and provides the necessary management information. The following sections then cover the material in a detailed manner.
Control Data needs no formal introduction to the Atlas Computer Laboratory; both organisations are each well aware of the others reputation and competence in the field of large scale computing systems.
Control Data will be pleased to enter into discussions about this proposal, which is of course not a contract but is an invitation to enter into a contract. The terms of this proposal will remain valid for a period of 120 days after the receipt of the document; the spirit of the proposal will naturally be valid until such time as the Atlas Computer Laboratory has chosen equipment to meet its requirements.
Taffeta phrases, silken terms precise
Three-piled hyperboles, spruce affectation.
Figures pedantical.
(Loves Labour's Lost. V.ii. 407)
Control Data proposes the advanced STAR computing system to meet the computation needs of the Atlas Computer Laboratory.
The STAR computer is the outcome of a lengthy research and development program within Control Data. The resulting machine, although owing a great deal to the CDC 6600 and 7600 computers, essentially provides a radical departure from previous computer designs. Used conventionally, the STAR-100 processor performs at about the level of a 7600 computer. Fully exploited, the machine can achieve over a factor of four more than this, and in certain applications up to a factor of ten. The machine and its attributes is described in more detail later in this document. The relevance to the Atlas Computer Laboratory requirements includes:
The proposed configuration is shown in figure 1.1. This configuration shows a STAR-100 and a STAR-1B processor, sharing access to a storage station and with both processors connected to two service stations. These service stations are in turn both connected to the second level peripheral stations, which include a high speed batch station with card readers, a card punch and line printers, a display station with seven interactive display/keyboard terminals and a communications station. The STAR-100 has associated with it a maintenance and measuring station and a paging station. One service station also performs the functions of maintenance and paging for the STAR-1B processor.
The present plans of Control Data allow for the delivery of this entire installation to be complete by the end of 1974 with the exception of the high performance advanced drum. For this unit, the intention is to attach the advanced drum system to STAR-100 by the 40 megabyte per second direct memory access channel. However, on delivery the drums will use two normal 5 megabyte per second channels. At this time, production schedules on the drum make it possible that earliest delivery would be in 1975, in which case the well proven Control Data 865 drums will be delivered for the interim period. This is described further in section 2 of this proposal.
The features of this configuration have been briefly enumerated. Attention should be given to the cross connections of vital data paths to aid in continuous provision of service and also to the important role of the small STAR-1B processor. With most computer installations it is common for the system to be out of use for an hour or more each day for the purpose of operating system development. This configuration allows operating system development and even research to proceed during normal computing service.
Control Data proposes to deliver the STAR-1B with a service station and two peripheral stations by the end of 1973. The configuration for this is shown in figure 1.2. Because of the newness of the STAR computing system, this configuration can be of inestimable worth to the Atlas Computer Laboratory in the areas of user education, internal training and software development. An interim upgrading can be made to the configuration shown in figure 1.3 early in 1974 at the convenience of the Atlas Computer Laboratory. This upgrading adds more peripherals to the high speed batch station and establishes the permanent file system.
The following is a brief description of the major components of the system.
Control Data has been developing software for the STAR computer for a number of years. At this time there are a number of complete software products, a number of projects under development that will become products in due course and a number of projects of a very experimental nature, the outcomes of which are difficult to predict accurately.
In the first group are included:
In the second group are included:
In the experimental class are:
The 6600 compatible FORTRAN compiler was being developed by Neil Lincoln
The basic software that Control Data will provide is such that the Atlas Computer Laboratory can be assured that the system is on a firm basis and, even by the time of delivery of STAR-1B, it will meet many of their requirements. By the time of STAR-100 delivery a sophisticated software product will be available, and this is described further in Section 4. However, Control Data recognises that most large computer installations have specialised requirements over and above a general software product. The Company therefore intends to provide a number of support analysts whose charter with be both to maintain the standard software and to assist the Atlas Computer Laboratory in making additions that it feels are necessary.
Control Data is well aware of the difficulties involved in the advent of a new large scale computer of novel architecture; these problems are not new to it and the Company attaches great importance to making a resounding success of the early STAR-100 installations. It has found it expedient and mutually beneficial to enter into joint software development arrangements with the first two STAR-100 customers, and wishes to propose that the Atlas Computer Laboratory also becomes involved in such a project. The obvious area for mutual joint development is in the provision of compilers for languages that allow problem algorithms to be expressed in ways that match the hardware provided. A major example here is the Algol-68 language; another, though to a lesser extent, is Algol-60. There are alternative projects that Control Data would like to pursue, including a user orientated measurement and monitoring system.
In exchange for such a project, and for the rights to maintain, document, and provide the outcome as a Company product, Control Data intends to make two offers.
The first of these is to price the STAR-1B very favourable, and the second is to make a substantial development grant. Both of these offers are in recognition of the following facts:
Control Data will of course enter into the normal firm commitments for STAR-100 software. However, during the period that STAR-1B is the only machine.involved, the Company would prefer the software to be regarded as being of final development status. This will enable tailoring of the product to meet specific requirements of the Atlas Computer Laboratory.
Total purchase price of equipment subject to agreement on a suitable development project:
£3,938,500
The itemised list below shows the component costs and the annual maintenance charges for single prime shift working.
| Component | Pricing in £ | Annual Maintenance in £ |
|---|---|---|
| STAR-100, with STAR-1B and 1B service station | 3,596,000 | 93,120 |
| Advanced Paging station | 426,000 | 17,760 |
| Service station | 153,250 | 7,488 |
| Storage station | 130,250 | 5,880 |
| 2 access MT control | 26,900 | 1,507 |
| 6 × MT 9 track | 101,250 | 4,838 |
| 2 × MT 7 track | 35,800 | 1,507 |
| 8 × 844 disk drives | 86,100 | 3,840 |
| 8 × 881 removable packs | 3,050 | |
| High speed batch station with CR/LP | 43,400 | 3,273 |
| 1 × CR 1200 cpm | 6,900 | 432 |
| 1 × LP 1200 lpm | 16,100 | 1,248 |
| 1 × CP 250 cpm | 7,600 | 480 |
| 2 × print train 595-6 ANSI set | 2,400 | |
| 1 × display/keyboard | 1,200 | 96 |
| Display station with 7 CRT | 78,800 | 4,608 |
| Communications station | 21,100 | 720 |
| 16 adaptors to 96K baud | 2,400 | 153 |
| TOTAL | 4,738,500 | |
| Less research/development grant | 800,000 | |
| TOTAL | 3,938,500 | 146,950 |
The charges for additional second, third and fourth shift maintenance cover consists of the basic prime shift price plus 10%, 2O% and 30%. The maintenance price includes prime shift analyst support. Control Data reserves the right to charge for software after 1975. The duties of support engineers and programmers are discussed in Section 6.
The cost of maintenance of the initial delivery is as follows:
| Component | Annual Maintenance in £ |
|---|---|
| STAR-1B | 19,608 |
| 1B Service Station | 6,494 |
| High speed batch station | 3,369 |
| Display station | 4,608 |
| TOTAL | 34,079 |
The additional maintenance charge after the interim delivery will be:
| Component | Annual Maintenance in £ |
|---|---|
| Storage station complete | 17,572 |
| CR, LP, CP | 2,160 |
| TOTAL | 19,732 |
Control Data proposes that the total of £3,938,500 be paid in four annual installments, three of one million pounds with the fourth being the balance owed.
As a basis for negotiation, the Company proposes:
Payment Date £1,000,000 April, 1973 £1,000,000 April, 1974 £1,000,000 April, 1975 £ 938,500 April, 1976
Sensible alternatives might be on receipt of order, initial delivery, interim delivery and final acceptance. However, the above procedure is possibly more convenient for the Science Research Council.
Control Data provides many supporting services to help create and maintain a high professional standard. These are summarised below and described further in section 6.
If this were played upon a stage now,
I would condemn it as an improbable fiction.
(Twelfth Night, lll.iv. 142)
The Control Data STAR-100 computer is a large scale, high-speed, logical and arithmetic computing system. The STAR-100 computer Utilizes many advanced design features such as stream processing, integrated circuitry, virtual addressing, hardware macro instructions, and a high density logic hardware register file. The STAR-100 computer also contains stream arithmetic and functional units especially designed for sequential and parallel operations on single bits, 8-bit bytes, and 32-bit or 64-bit floating point operands and vectors. The virtual addressing method employs a high-speed mapping technique to convert a logical address to an absolute storage address.
The basic computing system (figure 2.1) consists of a central processor interconnected to the standard magnetic core storage (MCS) unit, the eight input/output channels, and the high-speed, direct access channel.
The central processor contains all streaming and instruction control, arithmetic units, storage access control, and input/ output communication control, including control for the direct access channel. The standard MCS contains 524,288 64-bit words of storage. The MCS consists of eight physical sections with each section connecting to 132-bit (128 data bits and 4 parity bits) read and write data busses. Each MCS section contains four banks, giving a total of 32 multiphased banks. An optional MCS, identical to the standard, can provide an additional 524,288 64-bit words, giving a total system capability of 1,048,576 64-bit words.
The maintenance station connects to input/output channel 1. The maintenance station consists of a peripheral station with special maintenance control and monitoring capabilities.
Each of the seven additional input/output channels provides 16-bit communication and control to a peripheral station. The peripheral stations consist of a buffer controller and related control circuitry connected to the corresponding peripheral equipment. The buffer controller allows a great deal of flexibility in the selection of peripheral equipment connected to it, in that the software driver programs perform the functions previously done by separate peripheral controllers. A typical peripheral station might be connected to a line printer, a card reader, and some magnetic tape units. As shown by Figure 2.1, additional input/output channels may be added to the system up to a total of 12.
In addition to the eight input/output channels, the basic system includes a 128-bit direct access channel. This channel provides very high-speed communication directly to the MCS. For example, it can be connected to a mass storage device such as a disk or drum system, and give up to a 40 megabyte/second transfer rate.
The central processor unit (CPU) (Figure 2.2) consists of four main units as follows:
This section describes the general operation of each of these functional areas. In addition, it describes some special operational registers and counters and concludes with a brief description of the hardware features in the central processor unit.
The storage access control (SAC) unit controls the transmission of data to/from MCS and performs virtual address comparison and translation. The SAC unit also generates parity bits for write data and checks parity for read data. Thus, SAC provides access to MCS for stream, the I/O channels and the direct access channel.
The SAC unit (Figure 2.2) reads and writes data on eight independent read and write busses. In this case, a bus is defined as a physical grouping of cables and associated circuits used to carry data. If the optional MCS is connected to the system, a total of 16 read and write busses are available for data transmission to/from MCS. For each reference, the data transmissions to/from MCS are in the form of four 132-bit portions of the 528-bit superword ("sword") contained in the MCS. Each 132-bit portion is referred to as a 1/4 sword and consists of 128 data bits and 4 parity bits. One parity bit is associated with each 1/2 word of data.
The SAC unit contains three read accesses. An access is defined as a grouping of one or more busses which share a selection network for accessing the MCS busses. Read busses 1, 2 and 3 provides read access for the stream unit. These three read busses provide instructions, operands, addresses, and control information to the stream unit for control and distribution to the floating point and string functional units. A single 128-bit read bus is provided for the direct access channel. The 128-bit, read data 1/4 swords for the I/O channels are disassembled in SAC and are transmitted to the requesting I/O channel as 16-bit bytes. The direct access channel and the I/O channels share read access 3 with the stream unit. Read access 1 is shared by the stream unit and the associative registers in SAC. Read access 2 is used exclusively by the stream unit.
On read operations, SAC performs an odd parity check on each 1/2 of data. If a parity fault is detected, the parity fault condition is set. Tne resulting operation depends on the access input that requested the data containing the parity fault as described later. If no parity fault is detected, the data is transmitted to the input that made the request. In all requests except the requests associated with read bus 3, only the data bits are transmitted. Since instruction words are transmitted over read bus 3, the SAC unit first checks the parity in the normal manner and then transmits the 128 data bits with the corresponding parity bits to the stream unit for further checking.
When a parity fault is detected, SAC stores the type of parity fault and the absolute address of the data causing the fault in a register which can be read by the maintenance station. However, in the case of stream instruction parity faults, the faults are detected just before the instruction is executed which is far too late to store the absolute address of the fault. In this case, the current instruction address register (in the stream unit) contains the virtual address of the instruction that caused the parity fault. It is possible to determine the absolute address from this virtual address if it is needed.
If two or more parity faults occur before the maintenance station can analyze and clear each fault individually, only the address of the first fault is stored on SAC. The SAC accumulates and stores the type of parity fault for each parity fault detected.
Six types of parity faults are detected, as listed below. The CPU deals directly with input/output channel parity failures. For all others the maintenance station analyses the event, and eventually clears the fault and restarts the central machine.
The SAC unit contains two write accesses (Figure 2.2). Write busses 1 and 2 provide two inputs for the stream unit access to MCS. These two write busses transmit result operands and other output data from the stream unit to SAC for storage in MCS. A single 128-bit write bus is provided for the direct access channel. The SAC unit assembles the 16-bit bytes transmitted from the I/O channels into 1/4 swords and transmits these to MCS. The direct access channel and the I/O channels share write access 1 with the stream unit. Write access 2 is used exclusively by the stream unit.
In write operations, the SAC unit generates the four parity bits for each 1/4 sword. The format of the write data, as transmitted to MCS, is identical to the read data as shown in Figure 2.2.
The SAC unit contains the 16 associative address registers and corresponding control circuits. Except when the CPU is in the monitor mode, all storage addresses sent from the stream unit are virtual addresses. The SAC unit compares a virtual address with the corresponding portion of the associative address registers. If a match is found, the virtual address control circuits convert the virtual address into the corresponding absolute storage address from which the reference is made. If no match is found in the associative address registers, the virtual address control circuits read additional associative words from a restricted portion of MCS, termed the space table.
For virtual address references, there are two MCS page sizes available; the 65, 536 and the 512 64-bit word pages. The page sizes are selectable under program control and are applicable only for virtual address references.
The SAC unit contains the storage protection circuits for the STAR system. The storage protection features consist mainly of a lock and key arrangement. Each associative word contains a 12-bit lock code. The lock code is associated with a page of MCS. Each job is assigned four 12-bit keys by monitor. If a virtual address matches the corresponding portion of the associative word, the four keys associated with the current job are compared with the lock code in the matching associative word. One of the four keys must match the lock code before the storage reference can be completed. Thus, the Monitor program can restrict MCS page access to only the specified jobs by assigning the lock and key codes accordingly.
In addition to the key/lock protection feature, each of the four keys is associated with a 4-bit usage lockout code. This code can lock out CPU write operations, CPU read operations and/or CPU instruction references. If a key matches the lock of an associative word, but the requested type of reference is inhibited by the usage lockout code, an access interrupt takes place to the Monitor program. Thus, the Monitor program can restrict MCS page access for a job to a particular type of reference.
Since during monitor mode- all CPU references are absolute addresses, the storage protection features are disabled for these references. In the same manner, all direct access channel and I/O channel references are absolute addresses and are unrestricted by the storage protection features.
The stream unit provides basic control for the computer. The unit:
The stream unit interfaces with the storage access control (SAC), floating point unit 1 via pipeline 1 (full duplex), floating point unit 2 via pipeline 2, string unit (business data processing arithmetic unit), and the maintenance station for maintenance and fault monitoring (Figure 2.2).
The stream unit (Figure 2.3) contains a register file (RF) of 128 locations (128 bits each) which is used for instruction and operand addressing, indexing, field length counts, and as a source or destination for register-type instruction operands or results. The register file, which is composed of two 64-word by 128-bit high density logic (HDL) is also treated as the first 256 words of central storage for any program. The monitor program transfers the contents of these central storage locations to the register file prior to entry into the job program. The return transfer occurs upon termination of the job program.
Instruction control receives all instructions from central storage via read bus 3 or from the register file in stream. The rate of instruction issue is increased through use of buffering in instruction control. This buffer is a HDL storage instruction stack of 16 words of 128 bits each. Each request to central storage or the register file transfers one sword of instructions into four locations in the instruction stack. The next instruction request is sent when instruction issue from the most recently acquired sword of instructions begins. The program may branch forward in the instruction stack to any location in the same sword of instructions (or to the next sword after it is loaded into the stack). It may branch back in the stack to any executed instruction remaining in the stack which was loaded after the last branch out of stack. The instruction stack is effectively cleared upon branching out of the stack.
Each sword of instructions obtained from central storage via read bus 3 is accompanied by 16 parity bits which are stored in a group of 64. The hardware checks parity on each 32 bits of instruction at the time the instruction is read out of the instruction stack.
All operands for processing by the arithmetic units enter stream via the input stream and buffer control data paths (except for a few register instructions processed in stream). Operands from central storage enter via read bus 1 and read bus 2; operands from the register file are routed through transmit and output stream control.
The operands received at the inputs must be properly paired before arithmetic operations can proceed. A 4K-HDL storage buffer of 32 locations (128 bits each) or an 8K-buffer of 64 locations is available to temporarily hold either data input stream until operand alignment occurs. (The 4K buffer is used in most instances). While one of the buffers may be in use for input operand buffering, the other is available for use as an output buffer for write bus 1.
The transmit network provides a data path between the stream input and output data paths bypassing the floating point units. This path through transmit to the output stream control is used to:
The output stream control is a data routing network for arithmetic results returning from the floating point and string units and for instructions and operands originating in the register file.
Arithmetic results received from floating point units 1 and 2 and the 16-bit string interface are positioned and assembled in the output stream control before being stored in MCS via write bus 1 or in the register file. Buffering of result operands for write bus 1 occurs in one of the two buffers when required. Floating point multiply results from floating point unit 1 are temporarily stored in a separate four sword buffer (the other half of the instruction stack buffer) to permit their recombination with the delayed results from floating point unit 2.
A job program request for instructions or operands from the lower 128 quarter swords of central storage results in a reference to the register file. The quarter sword instruction word is routed from register file via transmit to the output stream section and on to instruction control. Similarly, the register file operand is routed through the output stream control to the input in the input stream and buffer control section.
The output stream control generates the virtual starting addresses for operand fields from the base addresses, offsets, and field lengths contained in the register file locations specified by the instructions. The addresses and field lengths are modified in the output stream control before being transmitted to SAC.
The output stream control also performs the addressing for instructions, operands for processing, arithmetic results, and order vectors or control vectors.
A transfer of one sword of data is associated with each storage request. Four minor cycles are required to transfer one sword of data on a bus. Through proper phasing of 32 storage banks, a storage request may be issued every minor cycle. Thus, four busses can access storage in a sequential manner without any time delay due to trunk conflicts or storage being busy. (A storage bank is busy for 31 minor cycles; a storage section of four banks per section is busy for four minor cycles on a bank request.
Write bus 2 is used for a register file exchange and storing the invisible package only. All other use of this bus must stop before a register file exchange can take place because all four busses are required for the two read and two write operations of the exchange.
Floating point numbers in STAR are two lengths, 32 bits and 64 bits. The 32-bit representation has an 8-bit exponent and a 24-bit coefficient (Figure 2.4). The 64-bit representation has a 16-bit exponent and a 48-bit coefficient. The left-most bit of each exponent and coefficient is the sign bit.
The floating point arithmetic section of STAR is divided into two units or pipes (Figures 2.5 and 2.6). Pipe 1 is used for register add, register subtract, register multiply, and all vector arithmetic instructions except divide and square root. Pipe 2 is used for register divide, register square root, and all vector instructions. This organisation of hardware allows optimum performance for both register and vector divide operations.
The floating point unit(s) receive operands from the stream unit. After performing the instructed arithmetic operation, the results are returned to stream. The exponent and coefficient paths through pipe 1 are shown in Figure 2.5.
For addition and subtraction operations, the input exponents are compared in the exponent compare circuit. The difference in the two exponents is used as a shift count which determines the amount the coefficient with the smaller exponent is right shifted in the coefficient alignment section. The coefficients are added in the add section. If the operation being performed specifies normalization, the result of the add operation is fed to the normalize count. This circuit produces a shift count which controls the normalize shift network and modifies the result exponent. The shifted result is returned to stream by the transmit circuit.
If normalization is not specified, the result of the add operation is the desired result and is transmitted to stream.
If the instruction is a multiply, the operands are multiplied in the high speed multiply unit. The result of the multiply is either returned directly to the transmit section or to the normalize count logic for normalization. The normalize count functions only for the multiply significant instructions.
Any result from pipe 1 may be returned directly to either of the inputs of pipe 1 if the result is needed as an input operand. This process is called shortstopping and eliminates the time necessary to store the result in the register file and then to read it out.
Pipe 2 is used for register divide, register square root and all vector instructions (Figure 2.6). The add pipe is similar to the add pipe line in pipe 1. The register divide portion of pipe 2 is a single segment divider. This divide unit also performs the binary to BCD and BCD to binary conversion.
The multi-purpose portion of pipe 2 performs the square root, vector divide, and 1/2 of the vector multiply instructions. The multipurpose unit is divided into 26 segments.
The string unit processes strings of decimal and binary numbers. Diagram 2.7 shows a block diagram of the unit. For details of its operation, the hardware reference manual should be consulted. The unit performs the operations of:
The following paragraphs give a brief description of some of the main operational registers and counters in the CPU, but not including the hardware registers used in the register file as these are described elsewhere.
The 64-bit data flag branch register (DFB) provides the programmer with an automatic branch to a special routine to obtain certain operands, results and conditions. This feature eliminates the time-penalty paid in explicitly checking the selected conditions in the program. If a previously selected automatic branch condition occurs during an instruction, the machine completes the instruction and stores the address of the next instruction in the address portion of register Ol in the register file. The program then branches to the address that was previously stored in register 02 of the register file.
The state of the data flags in the invisible package is defined only if the program was interrupted between instructions.
The CPU contains three counters that can be used for real-time programming applications: the free running clock, monitor interval timer, and job interval timer counters.
The first consists of a free running 48-bit counter that is incremented at a 1 MHz rate. The highest order bit is a sign bit. The free running clock counter is cleared by a power-on master clear.
The 24-bit monitor interval timer is a counter decremented at a 1 MHz rate when the computer is in the Monitor mode. The timer can be activated by loading it with any quantity other than all 0's. Once it is activated, the timer decrements at a 1 MHz rate until it reaches an all zero count. When the counter reaches a zero count, it causes an external interrupt on channel 15 which is processed like any other external interrupt. At this point the timer is deactivated until it is loaded with some value other than zero.
The job interval timer is a 24-bit counter decremented at a 1 MHz rate when activated by loading it with any value other than all 0's. The timer is then decremented until it reaches a zero count while the CPU is in the job mode. When the timer is decremented to zero, the CPU sets bit 36 in the DFB register. If the data flag mask bit is set at this time, a data flag branch takes place.
Each job has a location in its invisible package for the contents of the job interval timer. Once the timer is activated, it will be decremented while the job is being executed until the counter reaches zero or is deactivated. Note that the timer will not be decremented during Monitor mode.
The computer system contains special hardware features that allow the monitoring of system operation by the maintenance station. The hardware monitoring features include temperature, dewpoint and power monitoring and also counters that count special operational activities in the CPU. The hardware monitoring features communicate directly with the maintenance station over special monitoring control lines.
The system contains a temperature monitoring device. The temperature is monitored in each machine section. If the temperature in any section or the dewpoint in the room exceeds the safe limits set for the system, the monitor circuit rings an audible alarm and sends a signal to the maintenance station. Upon detecting signal, the maintenance station can halt the CPU. The CPU can recover operation when the faulty condition is corrected.
If no action is taken to correct the fault within 2 minutes, the monitoring circuit disconnects system power. The monitoring circuit locates the source of the fault.
In addition to the temperature-dewpoint monitor, each machine section contains a thermostat. If the temperature in a particular machine section exceeds the safe upper limit, the corresponding thermostat disconnects power in that section immediately.
The CPU contains two main power monitoring circuits: power fail and ripple detector circuits.
If the input power to the motor-generator drops for more than 10O ms, the 60-Hz power fail signal is transmitted to the maintenance station. Upon detecting this signal, the maintenance station can bring the CPU to a recoverable halt. The system power remains up for approximately 500 ms after the 60-Hz input power drops.
If 400-Hz power drops in any machine section, the section power fail signal is sent to the maintenance station. A short circuit in any section trips the corresponding circuit breaker and lights an indicator, locating where the short exists in the section. This set of indicators is contained on the enuciator panel in each section. A test switch on each panel tests the indicators.
All sections contain a ripple detector circuit that indicates when the power supply ripple factor has exceeded the specified safe limits.
The maintenance station uses two main mediums of monitoring system operation: special counters and the display register.
The CPU contains four 16-bit counters called A1,B1,A2,B2 that can count the occurrence of preselected events for monitoring purposes. Each counter can be connected to an event line by the maintenance station. It can be arranged for the counters to be active all the time, in monitor mode, job mode, for a particular program or for a class of programs. The events that can be monitored are listed in the following table.
The maintenance station can also monitor the output of two display registers, one containing the output of the current instruction address register and the other containing the output of the CPU register selected by the maintenance station. Its role in detecting error conditions and in maintaining the STAR-100 processor is described in the hardware reference manual.
| Event Codes (hexadecimal) |
Event Descriptions | |
|---|---|---|
| Counter A1/B1 |
Counter A2/B2 |
|
| 01 | Number of branches out of the instruction stack. | |
| 01 | Number of branches in the instruction stack. | |
| 02 | Number of instruction sword references. | |
| 02 | Total number of minor cycles during which execution was stopped while waiting for an instruction from central storage. This time does not include waits for jumps. | |
| 03 | Number of times that an issue of a register instruction has been blocked because of an operand-result conflict. | |
| 03 | Total number of minor cycles during which the issue of register instructions was delayed because of an operand-result conflict. | |
| 04 | Number of shortstop path (Floating Point section) usages. | |
| 05 | Number of space table searches. | |
| 05 | Number of 1/4 swords searched in space table searches. | |
| 06 | Number of exchanges caused by program force interrupts. | |
| 06 | Number of exchanges caused by external interrupts. | |
| 07 | Number of exchanges caused by access interrupts. | |
| 07 | Total number of exchanges. | |
| 08 | Number of Direct Access channel storage requests. | |
| 08 | Number of Direct Access channel storage requests accepted. | |
| 09 | Number of normal channel storage requests. | |
| 09 | Number of normal channel storage requests accepted. | |
| 0A | Number of CPU storage requests. | |
| 0A | Number of CPU storage requests accepted. | |
| 0B | Total number of storage requests. | |
| 0B | Total number of storage requests accepted. | |
| 0C | Number of vector instructions with result fields less than 64 words. | |
| 0C | Number of vector instructions with result fields between 65 and 8K words. | |
| 0D | Number of string instructions with result fields more than 8K words. | |
| 0E | Number of string instructions with result fields less than 8 bytes. | |
| 0E | Number of string instructions with result fields between 8 and 32 bytes. | |
| 0F | Number of string instructions with result fields of more than 32 bytes. | |
| 10 | Number of alignments greater than a certain constant. | |
| 11 | Number of normalizations greater than a certain constant. | |
| 11 | Number of right-shift normalizations. | |
| 12 | Number of times that a particular function code or a particular category of function codes is executed. The count condition is determined by the 8-bit select code and an 8-bit mask sent to the CPU on the Maintenance Station output channel 8. Whenever the select code bits and instruction function code bits are equal, corresponding to a 1 in the mask, the counter will be incremented. If the mask contains all 0's, all instructions will be counted. | |
| 12 | Time - 1 MHz rate. | |
| 13 | Number of vector instructions. | |
| 13 | Vector set-up time measure - the number of minor cycles that the CPU is buffering during set-up or during the completion on vector instructions. If the vector streams are set up so there are no storage conflicts, this count is zero. | |
The MCS system consists of 524,288 66-bit words (64 data bits and 2 parity bits), physically arranged as 65,536 528-bit words. For convenience of reference, the MCS sizes are referred to as 524K and 65K, respectively. Each 528-bit word is called a super word or sword, and is contained in two 264-bit planes. The MCS is divided into 32 banks, physically located in eight sections. Each section contains four banks as shown in Figure 2.8. For addressing considerations, one bank contains 2048 addresses of 528 bits each. This compares to 16,384 addresses of 66 bits each. Two planes are referenced simultaneously to read or write a 528-bit sword. A MCS option for another 524K may be added to the system. This would require an additional eight sections of MCS.
Notes:
(1) Each bank contains two 264-bit planes of 2K each.
(2) One bank equals 2048 addresses of 528 bits each or 16,384 addresses of 66 bits each
The MCS degradation feature allows normal operation of the system within a segregated part of MCS and allows maintenance programs to be run in the bad portion. Two MCS degradation options are available from the maintenance station with the 524K system.
Due to the interleaving of the MCS banks, the general failure of one bank results in one faulty sword occurring on a 32-sword period through sequential addresses. Should this general failure of a bank occur in a 524K MCS system, the Phase 16 signal line from the maintenance station can restructure MCS in a way that sequential addresses sweep through 16 banks rather than 32. This function segregates MCS into lower and upper blocks, one of which is composed exclusively of good memory locations.
The Swap 262K signal line from the maintenance station can cause either block to appear as lower 262K. The use of the Phase 16 feature causes an associated time penalty on certain instructions due to the lower order of bank interleaving.
If only a single memory location is faulty or the failure is restricted to a few pages, operations may continue without using the Phase 16 feature with its corresponding time penalty. This is accomplished by avoiding the defective pages. Note that certain monitor instructions and internal CPU operations produce absolute addresses. If these addresses reference defective MCS, it may be necessary to use the Swap 262K feature to move the absolute address references out of the defective area of MCS.
Instructions in STAR are 32 or 64 bits in length. There are ten general types, listed below with their abbreviations:
There are twelve formats for instructions. The following tables show these formats, explaining the notation and lists the instruction repertoire in an abbreviated form. The instruction list is grouped by type. In the first column is given the hexadecimal function code, and this is followed by the format type, the number of bits in the operand and a short description.
The CPU operates in two modes, namely job and monitor. In the first of these monitor instructions are illegal. Monitor mode is entered from job mode when an interrupt is accepted or the exit force instruction is encountered.
| Designator | Format Type | Definition |
|---|---|---|
| A | 1 & 3 | Specifies a register that contains a field length and base address for the corresponding source vector or string field. |
| A | 2 | Specifies a register that contains the base address for a source sparse vector field. |
| A | C | Specifies a register that contains a two's complement integer in the right-most 48 bits. |
| B | 1 & 3 | Specifies a register that contains a field length and base address for the corresponding source vector or string field. |
| B | 2 | Specifies a register that contains the base address for a source sparse vector field. |
| B | C | Specifies a register that contains the branch base address in the right-most 48 bits. |
| C | 1,2 & 3 | Specifies a register that contains the field length and base address for storing the result vector, sparse vector, or string field. |
| C | C | Specifies the register that will contain the two's complement sum of (A) + (X) in the right-most 48 bits. The left-most 16 bits are cleared. |
| C+1 | 1 | The C + 1 designator specifies a register that contains the offset for the C and Z vector fields. |
| D | 9 & B | This two-bit designator specifies the branch conditions for the corresponding branch instructions. |
| E | 9 & B | This two-bit designator specifies the object bit altering conditions for the corresponding branch instructions. |
| F | 1-C | This 8-bit designator is used in all instruction format types to specify the instruction function code. This designator is always contained in the left-most eight bits of the instruction and is expressed in hexadecimal for all instruction descriptions. Thus, the function code range is 00-FF^g. However, not all of the possible function codes are used. |
| G | 1,2,3, 9, B & C |
This 8-bit designator specifies certain sub-function conditions for the corresponding instruction. The sub-functions include the length of the operands (32- or 64-bit), normal or broadcast source vectors, etc. The number of bits that are used in the G-designator varies with individual instructions . |
| I | 5 | The 48-bit I functions as an index used to form the branch address in a B6 branch instruction. In the BE and BF index instructions, I is a 48-bit operand. |
| I | 6 | In the 3E and 3F index instructions, I functions as a 16-bit operand. |
| I | B | In the 33 branch instruction, the 6-bit I-designator specifies the number of the DFB object bit used in the branching operation. |
| R | 4 | In the Register and 3D instructions, R specifies a register that contains an operand to be used in an arithmetic operation. |
| R | 5 & 6 | In the 3E, 3F, BE and BF Index instructions, R functions as a destination register for the transfer of an operand or operand sum. In the B6 Branch instruction, R specifies a register that contains an item count which is used to form the branch address. |
| R | 7, 8&A | In these format types, R specifies registers and branching conditions that are described in the individual instruction descriptions. |
| S | 4 | In the Register and 3D instructions, S specifies a register that contains an operand to be used in an arithmetic operation. |
| S | 7, 8&9 | In these format types, S specifies registers and branching conditions that are described in the individual instruction descriptions. |
| T | 4 | In this type of format, T specifies a destination register for the transfer of the arithmetic results, |
| T | 7,8,9&B | In these formats, T specifies a register that contains the base address and, in some cases, the field length of the corresponding result field or branch address. |
| T | A | In this format, T specifies a register that contains the old state of a register, DFB register, etc; in an index, branch, or inter- register transfer operation. |
| X | 1 & 3 | The X-designator specifies a register that contains the offset or index for vector or string source field A. |
| X | 2 | In this case, X specifies a register that contains the length and base address for the order vector corresponding to source sparse vector field A. |
| X | C | In the B0-B5 Branch instructions, X specifies a register that contains a signed, two's -complement integer in the right-most 48 bits which is used as an operand in the branching operation. |
| Y | 1 & 3 | The Y- designator specifies a register that contains the offset or index for vector or string field B. |
| Y | 2 | In this format, Y specifies a register that contains the length and base address for the order vector corresponding to source sparse vector field B. |
| Y | C | In the B0-B5 Branch instructions, Y specifies a register that contains an index that is used to form the branch address. |
| Z | 1 | In this format, Z specifies a register that contains the base address for the order vector, used to control the result vector in field C. |
| Z | 2 | In this case, Z specifies a register that contains the length and base address for the order vector corresponding to result sparse vector field C. |
| Z | 3 | In this format, Z specifies a register that contains the index for result field C. |
| Z | C | In the B0-B5 Branch instructions, Z specifies a register that contains a signed, two's -complement integer in the right-most 4-8 bits. This integer is used as the comparison operand in determining whether the branch condition is met. |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 3E | 6 | 64 | ENTER (R) WITH I (16) |
| 3F | 6 | 64 | INCREASE (R) BY I (16) |
| 4D | 6 | 32 | HALF WORD ENTER (R) WITH I (16) |
| 4E | 6 | 32 | HALF WORD INCREASE (R) BY I (16) |
| CD | 5 | 32 | HALF WORD ENTER (R) WITH I (24) |
| CE | 5 | 32 | HALF WORD INCREASE (R) BY I (24) |
| BE | 5 | 64 | ENTER (R) WITH I (48) |
| BF | 5 | 64 | INCREASE (R) BY I (48) |
| 38 | A | 64 | TRANSMIT R (00-15) TO T (00-15) |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 40/60 | 4 | 32/64 | ADD U; (R) + (S) TO (T) |
| 41/61 | 4 | 32/64 | ADD L; (R) + (S) TO (T) |
| 42/62 | 4 | 32/64 | ADD N; (R) + (S) TO (T) |
| 44/64 | 4 | 32/64 | SUB U; (R) - (S) TO (T) |
| 45/65 | 4 | 32/64 | SUB L; (R) - (S) TO (T) |
| 46/66 | 4 | 32/64 | SUB N; (R) - (S) TO (T) |
| 48/68 | 4 | 32/64 | MPY U; (R) * (S) TO (T) |
| 49/69 | 4 | 32/64 | MPY L; (R) * (S) TO (T) |
| 4B/6B | 4 | 32/64 | MPY N; (R) * (S) TO (T) |
| 4C/6C | 4 | 32/64 | DIV U; (R) / (S) TO (T) |
| 4F/6F | 4 | 32/64 | DIV S; (R) / (S) TO (T) |
| 63 | 4 | 64 | ADD ADDRESS R + S TO T |
| 67 | 4 | 64 | SUB ADDRESS R - S TO T |
| 58/78 | A | 32/64 | TRANSMIT (R) TO (T) |
| 59/79 | A | 32/64 | ABSOLUTE (R) TO (T) |
| 51/71 | A | 32/64 | FLOOR (R) TO (T) |
| 52/72 | A | 32/64 | CEILING (R) TO (T) |
| 5A/7A | A | 32/64 | EXP OF (R) TO (T) |
| 50/70 | A | 32/64 | TRUNCATE (R) TO (T) |
| 5B/7B | A | 32/64 | PACK R, S TO (T) |
| 5C | A | B | EXTEND R(32) TO T(64) |
| 5D | A | B | INDEX EXTEND R(32) TO T(64) |
| 76 | A | B | CONTRACT R(64) TO T(32) |
| 77 | A | B | ROUND CONTRACT R(64) TO T(32) |
| 7C | A | 64 | LENGTH OF R TO T |
| 53/73 | A | 32/64 | SIGNIFICANT SQUARE ROOT OF (R) TO (T) |
| 10 | A | 64 | CONVERT BCD TO BINARY, FIXED LENGTH |
| 11 | A | 64 | CONVERT BINARY TO BCD, FIXED LENGTH |
| 54/74 | 4 | 32/64 | ADJUST SIGNIFICANCE OF (R) PER (S) TO (T) |
| 55/75 | 4 | 32/64 | ADJUST EXPONENT OF (R) PER (S) TO (T) |
| 2A | 6 | 64 | ENTER LENGTH OF (R) WITH I(16) |
| 2B | 4 | 64 | ADD TO LENGTH FIELD |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 20/24 | 8 | 32/64 | BRANCH IF R = S (32/64 BIT F.P.) |
| 21/25 | 8 | 32/64 | BRANCH IF R ≠ S (32/64 BIT F.P.) |
| 22/26 | 8 | 32/64 | BRANCH IF R ≥ S (32/64 BIT F.P.) |
| 23/27 | 8 | 32/64 | BRANCH IF R < S (32/64 BIT F.P.) |
| 33 | B | 1 | DATA FLAG REGISTER BIT BRANCH AND ALTER |
| 3B | A | 64 | DATA FLAG REGISTER LOAD/STORE |
| 32 | 9 | 1 | BIT BRANCH AND ALTER |
| 36 | 7 | 64 | BRANCH AND SET (R) TO NEXT INSTRUCTION |
| 31 | 7 | 64 | INCREASE (R) AND BRANCH IF (R) ≠ 0 |
| 35 | 7 | 64 | DECREASE (R) AND BRANCH IF (R) ≠ 0 |
| 09 | 4 | 64 | EXIT FORCE |
| B0 | C | 64 | INDEX, BRANCH IF (A) + (X) = (Z) |
| B1 | C | 64 | INDEX, BRANCH IF (A) + (X) ≠ (Z) |
| B2 | C | 64 | INDEX, BRANCH IF (A) + (X) ≥ (Z) |
| B3 | C | 64 | INDEX, BRANCH IF (A) + (X) < (Z) |
| B4 | C | 64 | INDEX, BRANCH IF (A) + (X) ≤ (Z) |
| B5 | C | 64 | INDEX, BRANCH IF (A) + (X) > (Z) |
| B6 | 5 | NA | BRANCH TO IMMEDIATE ADDRESS [ (R) + I(48)] |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 80* | 1 | E | ADD U; A + B → C |
| 81* | 1 | E | ADD L; A + B → C |
| 82* | 1 | E | ADD N; A + B → C |
| 84* | 1 | E | SUB U; A - B → C |
| 85* | 1 | E | SUB L; A - B → C |
| 86* | 1 | E | SUB N; A - B → C |
| 88* | 1 | E | MPY U; A * B → C |
| 89* | 1 | E | MPY U; A * B → C |
| 8B* | 1 | E | MPY U; A * B → C |
| 8C* | 1 | E | DVD U; A / B → C |
| 8F* | 1 | E | DVD S; A / B → C |
| 83 | 1 | 64 | ADD A; A + B → C |
| 87 | 1 | 64 | SUB A; A - B → C |
| 98 | 1 | E | TRANSMIT A → C |
| 99 | 1 | E | ABSOLUTE A → C |
| 91 | 1 | E | FLOOR A; → C |
| 92 | 1 | E | CEILING A → C |
| 9A | 1 | E | EXP OF A → C |
| 90 | 1 | E | TRUNCATE A → C |
| 9B | 1 | E | PACK A, B → C |
| 9C | 1 | E | EXTEND A(32) → C(64) |
| 96 | 1 | E | CONTRACT A(64) → C(32) |
| 97 | 1 | E | ROUNDED CONTRACT A(64) TO C(32) |
| 93* | 1 | E | SIGNIFICANT SQUARE ROOT OF A → C |
| 94 | 1 | E | ADJUST SIGNIFICANT OF A PER B → C |
| 95 | 1 | E | ADJUST EXPONENT OF A PER B → C |
* These instructions have sign control capability.
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| A0* | 2 | E | ADD U; A + B → C |
| A1* | 2 | E | ADD L; A + B → C |
| A2* | 2 | E | ADD N; A + B → C |
| A4* | 2 | E | SUB U; A - B → C |
| A5* | 2 | E | SUB L; A - B → C |
| A6* | 2 | E | SUB N; A - B → C |
| A8* | 2 | E | MPY U; A * B → C |
| A9* | 2 | E | MPY L; A * B → C |
| AB* | 2 | E | MPY N; A * B → C |
| AC* | 2 | E | DVD U; A / B → C |
| AF* | 2 | E | DVD S; A / B → C |
* These instructions have sign control capability.
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| C0 | 1 | E | SELECT EQ; A = B, ITEM COUNT TO C |
| C1 | 1 | E | SELECT NE; A ≠ B, ITEM COUNT TO C |
| C2 | 1 | E | SELECT GE; A ≥ B, ITEM COUNT TO C |
| C3 | 1 | E | SELECT LT; A < B, ITEM COUNT TO C |
| DA | 1 | E | SUM (A0 + A1 + A2 + ... An) TO C AND C + 1 |
| DB | 1 | E | PRODUCT (A0, A1, A2, ... An) TO C |
| D5 | 1 | E | DELTA {A(N+1) - A(N)} → C(N) X |
| D1 | 1 | E | ADJ MEAN {A(N+1) + A(N)} / 2 → C(N) |
| D0 | 1 | E | AVERAGE {A(N) + B(N)} / 2 → C(N) |
| D4 | 1 | E | AVE DIFF {A(N) - B(N)} / 2 → C(N) |
| B8 | 1 | E | TRANSMIT REVERSE A → C(N) |
| DE | 1 | E | POLY EVAL {A(N)} PER B → C(N) |
| DF | 1 | E | INTERVAL A PER B → C |
| BA | 1 | E | TRANSMIT INDEXED LIST → C |
| B7 | 1 | E | TRANSMIT LIST → INDEXED C |
| DC | 1 | E | VECTOR DOT PRODUCT TO C AND C+1 |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| E0 | 3 | 8 | BINARY ADD; A + B → C |
| E1 | 3 | 8 | BINARY SUB; A - B → C |
| E2 | 3 | 8 | BINARY MPY; A * B → C |
| E3 | 3 | 8 | BINARY DVG; A / B → C |
| EC | 3 | 8 | MODULO ADD; A + B → C |
| ED | 3 | 8 | MODULO SUB; A - B → C |
| FB | 3 | 8 | PACK ZONED TO BCD; A → C |
| FC | 3 | 8 | UNPACK BCD TO ZONED; A → C |
| E4 | 3 | 8 | DECIMAL ADD; A + B → C |
| E5 | 3 | 8 | DECIMAL SUB; A - B → C |
| E6 | 3 | 8 | DECIMAL MPY; A * B → C |
| E7 | 3 | 8 | DECIMAL DVD; A / B → C |
| FA | 3 | 8 | MOVE AND SCALE; A → C |
| F8* | 3 | 8 | MOVE BYTES LEFT; A → C |
| F9* | 3 | 8 | MOVE BYTES LEFT, ONES COMPLEMENT |
| EA | 3 | 8 | MERGE PER BYTE MASK A, B PER G → C |
| FD* | 3 | 8 | COMPARE BYTES A, B PER MASK FIELD C |
| FE** | 3 | 8 | SEARCH FOR MASKED KEY BYTE; A, B PER C, G |
| FF** | 3 | 64 | SEARCH FOR MASKED KEY WORD; A, B PER C, G |
| D6 | 3 | 1 | SEARCH FOR MASKED KEY BIT; A, B PER C, G |
| EE* | 3 | 8 | TRANSLATE A PER B → C |
| EF* | 3 | 8 | TRANSLATE AND TEST PER B → C |
| D7* | 3 | 8 | TRANSLATE AND MARK A PER B → C |
| EB | 3 | 8 | EDIT/MARK A PER B → C |
| E8 | 3 | 8 | COMPARE BINARY A, B |
| E9 | 3 | 8 | COMPARE DECIMAL A, B |
* Delimiters may be used with this instruction. Automatic index incrementing also takes place.
** Automatic index incrementing takes place for these instructions.
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| F0 | 3 | 1 | LOGICAL EXCLUSIVE OR A, B → C |
| F1 | 3 | 1 | LOGICAL EAND A, B → C |
| F2 | 3 | 1 | LOGICAL INCLUSIVE OR A, B → C |
| F3 | 3 | 1 | LOGICAL STROKE A, B → C |
| F4 | 3 | 1 | LOGICAL PIERCE A, B → C |
| F5 | 3 | 1 | LOGICAL IMPLICATION A, B → C |
| F6 | 3 | 1 | LOGICAL INHIBIT A, B → C |
| F7 | 3 | 1 | LOGICAL EQUIVALENCE A, B → C |
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 3D | 4 | 64 | INDEX MULTIPLY R * S TO T |
| 3C | 4 | 64 | HALF WORD INDEX MULTIPLY R * S TO T |
| 5E | 7 | 64 | LOAD T PER S, R |
| 5F | 7 | 64 | STORE T PER S, R |
| 7E | 7 | 64 | LOAD T PER S, R |
| 7F | 7 | 64 | STORE T PER S, R |
| 12 | 7 | 64 | LOAD BYTE T PER S, R |
| 13 | 7 | 64 | STORE BYTE T PER S, R |
| 39 | A | 64 | TRANSMIT REAL-TIME CLOCK TO T |
| 3A | A | 64 | TRANSMIT R TO JOB INTERVAL TIMER |
| BB | 2 | 64 | MASK A, B → C PER Z |
| BC | 2 | 64 | COMPRESS A → C PER Z |
| CF | 1 | 64 | ARITH COMPRESS A → C PER Z |
| BD | 2 | 64 | MERGE A, B → C PER Z |
| 14 | 2 | 64 | BIT COMPRESS |
| 15 | 1 | 64 | BIT MERGE |
| 16 | 1 | 64 | BIT MASK |
| 17 | 1 | 64 | CHARACTER STRING MERGE |
| DD | 1 | 64 | SPARSE DOT PRODUCT TO C AND C+1 |
| C4 | 1 | 64 | COMPARE EQ; A = B, ORDER VECTOR → Z |
| C5 | 1 | 64 | COMPARE NE; A ≠ B, ORDER VECTOR → Z |
| C6 | 1 | 64 | COMPARE GE; A ≥ B, ORDER VECTOR → Z |
| C7 | 1 | 64 | COMPARE LT; A < B, ORDER VECTOR → Z |
| C8 | 1 | 64 | SEARCH EQ; A = B, INDEX LIST → C |
| C9 | 1 | 64 | SEARCH NE; A ≠ B, INDEX LIST → C |
| CA | 1 | 64 | SEARCH GE; A ≥ B, INDEX LIST → C |
| CB | 1 | 64 | SEARCH LT; A < B, INDEX LIST → C |
| D8* | 1 | 64 | MAX OF A TO C; ITEM COUNT → B |
| D9* | 1 | 64 | MIN OF A TO C; ITEM COUNT → B |
| B9 | 1 | 64 | TRANSPOSE/MOVE |
| 18 | 8 | 64 | MOVE BYTES RIGHT (R) + (T) → (R) + (S) + (T) |
| 19 | 8 | 64 | SCAN RIGHT |
| 28 | 8 | 64 | SCAN EQUAL |
| 29 | 8 | 64 | SCAN UNEQUAL |
| 1A | 8 | 64 | FILL FIELD T WITH BYTE R |
| 1B | 8 | 64 | FILL FIELD T WITH BYTE (R) |
| 1C | 1 | 64 | FORM REPEATED BIT MASK WITH LEADING ZEROS |
| 1D | 1 | 64 | FORM REPEATED BIT MASK WITH LEADING ONES |
| 1E | 1 | 64 | COUNT LEADING EQUALS R |
| 1F | 1 | 64 | COUNT ONES IN FIELD R, COUNT TO T |
| 04 | 64 | 64 | BREAKPOINT (MAINTENANCE) |
| 06 | NA | 64 | FAULT TEST (MAINTENANCE) |
* These instructions have sign control capability.
| Inst Code |
Format Code |
No. of Bits in Operand |
Instruction Title |
|---|---|---|---|
| 00 | 4 | NA | IDLE |
| 08 | 4 | 64 | INPUT/OUTPUT PER R |
| 0C | 4 | 64 | STORE ASSOCIATIVE REGISTERS |
| 0D | 4 | 64 | LOAD ASSOCIATIVE REGISTERS |
| 0E | 4 | 64 | TRANSLATE EXTERNAL INTERRUPT |
| 0F | 4 | 64 | LOAD KEYS FROM R, TRANSLATE ADDRESS S TO T |
| 0A | 4 | 64 | TRANSMIT (R) TO MONITOR INTERVAL TIMER |
The STAR-1B processor is a small computer that emulates the STAR-100 by microcoding techniques.
The basic computer consists of:
The microcode storage consists of thirty-two planes of memory. These planes store information by using capacitive coupling patterns on data sheets inserted between them. To change the microcode, these data sheets have to be physically replaced. It is possible to execute microcode instructions from the normal core storage, by a console selection switch. The 128 bit word is divided into 26 fields, each of which controls a specific part of the central processor.
The distribution of input/output functions into stations is achieved with hardware control units and buffer units.
The station control unit (SCU) consists of a buffer controller processor, a microdrum and a display/keyboard device with its associated controls.
The buffer controller is an internally programmed, parallel mode digital computer containing a minimum of 8 thousand bytes of core storage. Its instruction set is specifically chosen to handle the tasks involved with data transfers. The core storage can be any speed between 1.1 microseconds and 200 nanoseconds. The buffer controller has one 16-bit parallel block transfer channel and 16 full duplex 16-bit programmable input/output normal channels.
The microdrum provides memory extension for the buffer controller. It is used in the stations for storage of data, program overlays and display images, and provides an autoload. The microdrum is under direct control of the buffer controller and is accessed by the buffer controller1 on normal channels. The drum has 36 data tracks plus four control tracks, the data tracks being matrixed in three groups of 12 heads each. Two of these groups (24 heads) contain lockout protection controlled from the maintenance panel.
The rotation rate of the microdrum is 3600 revolutions per minute (17 milliseconds per revolution) with a bit recording frequency of 1 megahertz. The data is recorded serially in phase modulation. The nominal capacity of the unit is 16,000 bits per track with a total of 576,000 data bits.
Two storage formats are used with the microdrum: display format and data format. In data format, the data is recorded in 18 sectors per track. Each section contains 64 16-bit words. This data is sector alterable. In display format, data is stored to match the display refresh timing and storage requirements. A single track holds a display image recorded in 576 sectors, each sector recording two 8-bit characters. This data is also sector alterable.
The display/keyboard is based on the CDC 211 Display, and has an 18-line, 64-character-per-line display and an ASCII keyboard. It provides a station display for performance analysis, operation diagnosis, and maintenance.
A character generator within the control unit generates the 64-character ASCII set for the display keyboard. (The character generator used with the display station generates the full 96-character ASCII set.) The keyboard uses a standard typewriter keyboard arrangement, but includes the full 64-character ASCII symbol set (96-character set for the display station). It also includes four cursor control keys, 10 function keys and four mode keys. The station software controls the use of these keys.
The buffer unit consists of a core memory and the core control logic to provide the various access to the core. The core memory contains 32,768 16-bit words organised in eight phased banks. The memory cycle time of each bank is 1.1 microseconds. Figure 2.10 shows the arrangement of core memory and logic.
Up to 12 accesses (dependent upon station function).
The buffer unit is used in stations that have significant data flow. In these stations data transfer takes place using the buffer unit, freeing the buffer controller for higher-level control activities and providing more effective management of the data flow. The buffer unit is treated as an external memory to the buffer controller and is not directly addressable by the buffer controller. The control unit attaches to the buffer unit using its block transfer channel.
The 12 memory accesses can operate simultaneously. Request conflicts are resolved by the request scan logic which uses a simple number priority, with access 0 as high priority and access 11 as low priority. Normal channel bits from the buffer controller are available such that scan logic can have software control.
The service station (Figure 2.11) allows for extension of the STAR data channels to second-level stations which, in turn, control their respective peripheral devices and mass storage units.
The service station consists of a buffer unit, a control unit, a 45-million-bit drum unit, and eight input/output interfaces to an agreed Control Data/International Computers Ltd. specification.
The station is self sufficient in the sense that it is capable of loading and executing instructions in the buffer controller.
The STAR-100 service station provides a proper interface between the central computer system and the peripheral system. The service station performs the roles of:
The dual STAR interface provides for attachment to two central processors in a dual system. All data transfers between the data channel interfaces, the 45-million-bit drum, and central core take place using the station buffer unit. The service station data channel interfaces attach to peripheral stations. Logical communication between the service station and the attached stations is through messages.
The 5.6 megabytes drum unit, with 12-head parallel operation, provides for a 3 megabytes/second nominal data rate. The leading characteristics of the drum unit are:
The STAR-1B service station (Figure 2.12) performs first-level peripheral control for the STAR-1B system, controlling access of its connected peripheral units and second-level stations to the STAR-1B memory through storage access control input/output channels. The service station allows for extension of the storage access control input/output channels to second-level stations which, in turn, control their respective peripheral devices and mass storage units. In addition, for basic STAR-1B configurations, the station can provide the permanent file storage and act as a paging station.
The 1B service station consists of a buffer unit, a control unit, an 841 multiple disk drive, and four STAR-type interface channels.
The characteristics of this station are the same as for the STAR service station except that the 841 disk drive is substituted for the 5.6 megabyte drum. The 841 multiple disk drive provides paging, file storage and input/output staging.
Characteristics of the 841 multiple disk drive are:
ASCII modified characteristics are:
The maintenance station consists of a SCU with a card reader, line printer and two magnetic tapes. It also has some special channels to the STAR-100 central machine, allowing control of some maintenance and monitoring logic.
The functions of the maintenance station are, with respect to STAR-100
With respect to the system, the maintenance station also:
The paging station provides an extension to the central machine memory within the virtual memory mechanism. Although the file storage and input/output areas are managed within virtual memory, the paging station is uniquely concerned with being an extension of central memory. As such it has extra hardware for translating virtual page addresses into physical drum addresses. The station consists of two drums, each of 64 megabytes capacity and each transferring into a separate SBU with one SCU controlling the system. Each SBU is connected to a STAR channel. It is intended that the drums will be upgradeable to transfer into the STAR direct access channel, giving one transfer at 40 Mb/s instead of two in parallel at 5Mb/s each. Figure 2.13 shows the station diagrammatically:
The characteristics of the 270 drum are as follows:
The storage station provides file storage for the system. It consists of a SCU and SBU. The SBU has controllers as necessary for the storage devices attached, which may be fixed disk, removable disk packs or magnetic tapes. The station proposed to the Atlas Computer Laboratory has a two access controller attached to eight magnetic tapes and a two access controller attached to eight high performance multiple disk drives.
The 844 disk drives have the following characteristics:
The 659-4 9-track tape drives have the following characteristics:
The 657-3 7-track tape drives have the following characteristics:
The configuration for the Atlas Computer Laboratory proposes six 659-4 and two 657-3 tape drives.
The system functions performed by the average station include:
The high speed batch station consists of a SCU with fast (200ns cycle time) core storage and controllers for handling two card readers, two line printers and one card punch.
The station is normally attached to a service station.
It provides for:
The display station consists of a SCU and a modified SBU with interfaces for up to twenty-eight ANSI compatible character set display terminals of 18 lines at 64 characters each. These modifications to the SBU allow for all 28 terminals to have their displays continually refreshed from dedicated areas in the buffer storage. The functions performed by the station include:
The communications station consists of a SCU with 200 nanosecond cycle time core storage and logic for up to 48 communications adaptors. With the appropriate adaptors, the station can handle remote teletype compatible devices at speeds of 2400, 48OO or 9600 bits/second. The station includes a cyclic encode unit for error checking. It normally connects to a service station.
With all appliances and means to boot.
(Henry IV, part 2.III.i.29)
The proposed configuration is shown in Figure 3.1. It includes the equipment listed below.
The central processor includes:
Also included are
The physical layout of the central machine is shown in Figure 3.2.
Sections A, B, C, D, and E are the floating point units, F, G, H and J are the stream unit with the string unit and K, L and N are the storage access control unit. The core storage consists of sections MA to MH, each of 64 K words of 64 bits.
Each STAR section is 28.5 inches wide by 3O inches deep by 76 inches high. On top of each section is a removable power control module 6.5 inches high. Each STAR section contains 160 modules, consisting of two parallel 3 layer printed circuit boards to give 60 packages per module. Logic power is provided by 400 hertz supplies located in the base of each section. The modules are freon cooled, with the compressor for the refrigerant located external to the sections. The central machine contains an intercom system for maintenance purposes. Each section has a jack for a headset plug.
1 FV4O2B station control unit (SCU) consisting of 16K byte buffer controller processor,
4O megabyte micro-drum and display/keyboard with ASCII character set.
1 HR60O line printer at 600 lines/minute
1 430 card reader/card punch at 500 cpm and 1OO cpm respectively
1 609 9-track magnetic tape drive, at 3OK bytes/ second transfer rate,
800 bits per inch
1 FV402B/ SCU with 16K byte buffer controller (micro-drum and keyboard/display)
BB298A
2 FV228A Two station buffer units (SBU), each of 64K bytes in 8 phased banks,
1.1 microsecond cycle time and with interfaces for the
D270 advanced drum and for STAR channels
2 FA802A Two D270 drum controllers with virtual address mapping logic
2 D270 Two 27 inch drums, each of capacity 64 megabytes and with
one fixed head per track
The configuration shown for the paging station has two normal channels at 5 Mbytes/second, giving a peak drum transfer rate of 40 Mb/s. Control Data proposes to add an on-site enhancement to allow the drums to use the 40 Mb/s direct access channel, to give a 40 Mb/s peak rate with the same latency as before. This enhancement will be added at no charge and at the Atlas Computer Laboratory's convenience when it is fully operational. For a short initial period, the 27 inch drums may be unavailable because of production schedules. If this is the case Control Data intends to deliver, as an interim measure, two BG601A drums each of capacity 5.6 million bytes - the understanding being that these highly reliable devices will be of sufficient capacity for the first few months of the installation.
The STAR-1B central processor is a serial microded machine with 256K bytes of core storage. The microcoding, executed from a separate 32K bytes of read only storage consisting of capacitive data plates, gives an exact emulation of the STAR-100 central processor. The machine includes four input/output channels and certain hardware features to assist in efficient STAR emulation. Microcode can be executed from the central core storage at a reduced rate. Although the microcode is fixed, Control Data is willing to manufacture new data sheets to alter the coding if the Laboratory wishes to make changes.
The machine size is approximately that of four STAR sections. The functions of maintenance and of virtual memory extension are managed by the 1B-service station.
1 FV402B/ Station control unit with 16K bytes of core storage
BB398A
1 FV401A Station buffer unit
1 BG601A Magnetic drum storage of 5.6 megabytes capacity
The 12 SBU channels are used for one connection to the SCU, one to the drum, one to STAR-100, one to STAR-1B, and eight available for lower level stations. These are normally ICL/CDC standard channels and three of them are necessarily so; the remainder can be specified by the Laboratory.
1 FV402B station control unit
1 FV401A station buffer unit
1 841-3 Three 841 disk pack drives on one SBU channel with controller
including extra logic for mapping virtual addresses to disc addresses
The channels are as for the standard service station.
1 FV402B/ Station control unit with 16K bytes
BB398A
1 FV229A Station buffer unit
1 3528-3 Magnetic tape controller, using two SBU channels, giving
two independent channels for up to eight magnetic tape drives.
The drives may be any mixture of 7 and 9 track.
2 657-3 Two seven track magnetic tape drives, read and write at
150 inches per second, forward and reverse read at
200, 556 and 80O bits/inch and speeds of 30K, 83.3K and 120K
six bit chars/second.
6 659-4 Six nine track tape drives, read and write at ISO inches/sec,
forward and reverse read 80O and 16OO bits/inch, with speeds of
120K and 240K 8-bit bytes/second.
1 844C 844 disk pack controller, using two SBU channels, to give two
independent accesses for up to eight disk pack drives.
8 844-2 Eight 844 disk pack drives each of capacity 108 megabytes and
transfer rate 850K bytes/ second.
1 733-10 Basic SCU with one 1200 card/minute card reader and one 1200
lines/minute line printer. The 8K bytes of core storage has
200 nanosecon cycle time.
1 733-140 8K byte core storage increment
1 733-120 1200 cpm card reader
1 733-110 1200 lpm line printer
1 733-101 250 cpm card punch
2 595-4 Two line printer train cartridges of full 96 character ASCII set
1 733-152 Keyboard/display unit
1 FV402B/ SCU with 16K byte buffer controller
BB398A
1 FV228A/M Modified SBU with channels for attaching up to 48 display/entry
terminals, with automatic display regeneration
8 211/M Eight ASCII keyboard terminals, each with 18 lines of 64 characters display
1 791-1/ Communication station consisting of modified SCU with 16K bytes
10274-1 of 20O nanosecond core storage cyclic encode unit and interfaces
for 16 792 communication adaptors
16 792-2 16 adaptors to provide full duplex interface with communication lines
at speeds of 240O, 4800 and 960O bauds.
As well as teletype compatible devices, slow speed
remote job entry stations can be supported.
They have been at a great feast of languages,
and stolen the scraps.
(Loves Labour's Lost. V.i. 39)
The purpose of the STAR software is to provide a means of fully utilizing the STAR system; it is a framework within which users can exploit the machine characteristics.
The main features of the system are as follows:
The STAR operating system is divided into four parts:
The central monitor provides for:
The peripheral stations perform a number of general tasks to support the central system. These include:
Other types of functions are restricted to a class of stations. Some of these functions are listed below:
Software development for STAR has been in progress at a number of locations within Control Data, at the Lawrence Radiation Laboratory, Livermore, and at the General Motors Corporation, Detroit. The Company is currently engaged in the production of a unified software system for official release late 1972. This unified system is composed of elements from all the various groups involved in STAR development. The outcome will be a fully documented and maintained software set designed to be suitable for continuous building upon. It will initially contain the basic time sharing operating system, peripheral system, and those compilers and utilities that are in a stable finished state. The name of HELIOS is given to the system.
HELIOS version 0.5 will be released in August 1972. It will contain:
It is possible to install any software packages under HELIOS that conform to the STAR conventions. These conventions define program module format, register file useage, the linking mechanism and parameter passing methods.
It is expected that additions to HELIOS will fall into two classes, fully supported and partially supported.
The latter class includes:
These programs will be made available on an experimental basis.
The first class consists of production software much of which is in an advanced stage of development. The following list is not comprehensive and the dates in brackets are not commitments but the expected time at which the programs will be available.
For 'tis the sport to have the engineer
Hoist with his own petard.
(Hamlet, lll.iv. 206)
Control Data attaches great importance to system support and to the provision of services which help to ensure a continually successful installation.
The support Control Data offers to the Atlas Computer Laboratory is as follows:
The first three courses are at a general level. The remainder are aimed at experienced programmers and give detailed descriptions of the1 implementations. The operating systems are covered thoroughly/ and include overviews, flow charts, the instructions, system generation, installation parameters, and methods of adding new features.
These courses may be held at the Atlas Computer Laboratory or at the Control Data headquarters in London.
Control Data will provide an analyst team to support the installation. This team will be resident during the day-shift and may be on call at other times. The duties of the team will be.
Control Data will provide engineers to maintain the STAR hardware. The number of engineers provided will be at the discretion of the Company. The prime shift is regarded as being 06.00 to 17.00 hours. For eight hours of this, engineers will be on the site; for the remainder they will be on call. Charges for complete cover have been quoted in this proposal. The maintenance charges are subject to satisfactory performance of the machine, and credit is given when the system is inoperable if Control Data is responsible for the non-availability.
The STAR computer system is constructed of modern integrated circuits. As such, its reliability will be extremely good, for the main characteristic of the circuits is that they do not deteriorate as a function of time. Because of the nature of the circuits, it will be possible to power up and down the machine in any way without creating hardware problems.
However, it is a very large and powerful system and Control Data will need some dedicated preventive maintenance time daily until the machine is well settled in. By careful planning it can be arranged for computer service to continue in a degraded manner during these periods. The arrangements for this will be at the discretion of the Atlas Computer Laboratory. Every attempt-will be made by Control Data to establish maintenance procedures for the convenience of the Laboratory.
Control Data proposes to establish a department with complete responsibility for supporting the Atlas Computer Laboratory. The departmental manager of this will control the activities of the engineers, analysts, development staff and others concerned with the project. If possible, a Control Data office will be established local to the Laboratory.
In addition to this, the Company will appoint a senior staff member at Vice President level, to be responsible for liaison with the Laboratory at the top management level and to help ensure that the Laboratory is getting the supporting services that it needs. This member of senior staff will be available at any time for the Director of the Laboratory to contact; in addition he will visit the Laboratory at least once a year.
Control Data sponsors and supports the activities of a STAR users group. This group meets regularly to discuss all aspects of the STAR system. It makes recommendations on such subjects as hardware features, software structure, and compiler development; it defines conventions to be observed by those STAR installations wishing to share program modules and it strongly influences the Control Data policy on STAR development. The Company looks forward to welcoming the Atlas Computer Laboratory to this user group and assures them of its willingness to act upon any recommendations they may make at its meetings.
'Tis an ill cook that cannot
lick his own fingers.
(Romeo and Juliet. IV. ii. 6)
Control Data attaches great importance to the rapid and smooth installation of its computer equipment. For this reason the Company maintains a separate engineering department that specialises in site planning. This group will provide the Atlas Computer Laboratory with planning drawings specifically tailored to their installation, and well-suited as design guides. The drawings include a scaled floor plan and indicate the equipment location and floor arrangements. It also includes a power distribution diagram showing the exact wiring schedules, and a machine units specification that lists each cabinet and its associated physical properties, that is the dimensions, weight, heat dissipation and power consumption. In addition to this the site planning department will provide documented recommendations on all installation requirements, and as a service will advise freely and to the best of its ability any special requirements that the Atlas Computer Laboratory may have.
Because of the large amount of information to be transmitted, Control Data recommends that three formal meetings are scheduled between site planning department and the Atlas Computer Laboratory. These will be in addition to a number of informal meetings. The first formal meeting is with persons responsible for the computer's installation and operation. The purpose of this meeting is to acquaint the Atlas Computer Laboratory with the requirements of the STAR computer and to develop a floor plan which best suits the Atlas Computer Laboratory's needs. The second formal planning meeting is with the persons responsible for approval of the air conditioning, the power distribution, and the elevated floor systems. The purpose of this meeting is to ensure that the Atlas Computer Laboratory and Control Data are agreed in full detail with the plans and specifications that pertain to the design of a computer site and environment. During the third formal meeting, the site planning engineers will inspect the completed site to ensure that the work has been performed in accordance with these drawings and specifications.
The following table represents a schedule for site preparation activities:
Time before installation
CDC STAR-1B CDC STAR-100 Activity
2.5 months 9 months Conference No 1.
2 months 9 to 5 months Preparation of Design drawings
2 months 5 months Conference No 2.
2 months to 3 weeks 5 to 1 months Site preparation
1 month 5 weeka Conference No 3.
2 weeks 1 month Ship computer
0 0 computer ready for use
In order to achieve electromagnetic compatibility a grid-ground system consisting of AWG No.4 Copper wire (or AWG No. 2 or larger aluminium wire) forming a 2ft. by 2ft. network beneath the entire raised floor is required. In certain cases where a bolted stringer-type raised floor exists or is planned for, the wire grid-ground may not be necessary. This would be subject to the approval of the site planning department.
Quantities in the following sections are based upon the proposed configuration. Changes in the configuration will alter the quantities accordingly.
The following power is required:
The following factors must be considered when evaluating or designing the air conditioning system.
Industrial specifications for most elevated floors are 250 lb/ft. evenly distributed, and 1000 pound concentrated (2 in. diameter pad) load. Control Data equipment does not exceed this specification. Structural integrity of the false floor must not be affected by cable passage cut-outs.
Approximate floor area required for system: 1,300 sq.ft.
Customer Engineer area: 300 sq.ft.
Approximate well-ventilated equipment room floor area for two generator sets and their controllers: 200 sq.ft.
The following power is required:
The following factors must be considered when evaluating or designing the air conditioning system:
The temperature of some equipment is maintained by self-contained cooling packages which utilize water-cooled condensers or heat exchangers. The following factors must be considered when designing or evaluating the cooling water system:
Industrial specifications for most elevated floors are 250 lb/ft. evenly distributed, and 1000 pound concentrated (2in. diameter pad) load. Control Data equipment does not exceed this specification. Structural integrity of the false floor must not be affected by cable passage cut-outs.
Approximate floor area required for system: 3,845 sq.ft.
Customer Engineer Area: 500 sq. ft.
Approximate well-ventilated equipment room floor area for two generator sets and their controllers: 270 sq. ft.
Approximate well-ventilated equipment room floor area for two 30 ton condensing units: 25O sq. ft. (see location restrictions in Cooling Water section).
Approximate weight: 80,000 pounds.
The computer site should meet those standards as set forth in the National Fire Protection Association Leaflet No. 75, "Electronic Computer Systems". This document will be provided to you by the site planning department.
Past and to come seems best:
things present, worst.
(Henry IV, part 2. I.iii 108)
Control Data plans to enhance the STAR system, by a continual research and development project, over a number of years. The Company welcomes the opportunity of discussing the STAR research program with the Atlas Computer Laboratory. This research program is concerned with faster central processors, new upward compatible station processor designs and longer term peripheral and software developments.
This section describes some of those planned enhancements which have completed the design phase and are either in a late development stage or in preproduction.
At present the basic STAR-100 has 4 million bytes of core storage, extendable to 8 million bytes. An alteration extension, taking the same physical space, is the manybit memory of 256 million bytes. The main characteristics of this storage device are:
The 270 drums of 27 inches diameter, as proposed for the Atlas Computer Laboratory, currently transfer with two heads in parallel, each drum giving a five megabyte/second transfer rate. It is planned to transfer with 16 heads in parallel through the STAR direct access channel, to give a rate of 40 megabytes per second.
Development is continuing on the 540 drum of 54 inches diameter, for installations in need of a single drum with 128 million bytes capacity capable of transfer rates up to 160 megabytes/second.
A station is being developed for STAR to control disk pack drives of substantially higher performance than the current 841 and 844 devices.
The Scroll magnetic tape unit consists of a drive, a twenty two inch width magnetic tape, SBU and SCU.
The drive consists of two spools and a 24 inch diameter drum. By a series of control rollers, at any one time there is a 5 foot length of tape called a segment wrapped around this drum. The drum contains read/write heads, and transfers take place over one segment while the spools are stationary. The drum rotates continuously, at 1990 revolutions/minute. There are 2048 tracks for data across the magnetic tape; as many heads can be used in parallel to achieve any desired transfer rate.
In more detail, the characteristics of the scroll device are:
New software products will be produced continually to cover such subjects as:
This proposal has attempted to describe the STAR computer system in outline and to discuss a powerful configuration suitable for the requirements of the Atlas Computer Laboratory.
In a document of this nature there is only space for highlighting the system features; however, it is hoped that this will provide the basis for continued contractual discussions.
Control Data offers the STAR computer for sale to the Atlas Computer Laboratory with confidence. This confidence is based on the six years of STAR development work already made, and on a strong conviction that the proposed equipment can meet the Laboratory requirements for many years.
STAR is a new beginning, an exciting computer with a long life ahead of it. No doubt it still has some teething troubles ahead of it, and Control Data is well aware of the importance of having extremely professional establishments for the early installations. Such installations will benefit from the extra support Control Data will give, and will be able to direct the STAR project towards their specific needs. In the case of STAR, the Company can say with authority there are no major development problems remaining. By 1975, and probably well before, the system can be in a position to offer a comprehensive service for the Laboratory. Because Control Data realises there will be some initial problems, because the Atlas Computer Laboratory role closely matches the design aims of STAR, and because of the experienced background of the Laboratory, Control Data is offering a substantial educational and development grant. The Company also proposes that the STAR-1B system costing is at a very favourable price in exchange for a joint development project. The underlying hope with these offers is that the Atlas Computer Laboratory and Control Data can work together to provide a continuing successful environment, to the credit of the Science Research Council, for the benefit of university research, government scientific projects and all other users of the system.
Control Data would like to thank the Atlas Computer Laboratory for the opportunity to make this proposal, and to assure the Laboratory of its desire to serve it to the best of its ability.
Michael Baylis
Control Data Ltd