(Patents Pending)
Consider the normal arithmetical addition of two multi-digit numbers. Let one number be designated by the letter A, and the second by the letter B. These two numbers have to be added digit by digit. This digital addition must give rise to a sum digit S (say) and a carry digit C (say) which has to be added to the next digital addition. In general, therefore, three digits have to be added together each time, and a sequence of such digital additions has to be carried out in order to complete the addition of two multi-digit numbers.
Certain rules have to be obeyed when carrying out addition, and in the binary scale these rules are as shown in the following table:-
| Rule | Numbers to be added | Result | |||
|---|---|---|---|---|---|
| A | B | C1 | S | C2 | |
| 1 | 1 | 1 | 1 | 1 | 1 |
| 2 | 0 | 1 | 1 | 0 | 1 |
| 3 | 1 | 0 | 1 | 0 | 1 |
| 4 | 0 | 0 | 1 | 1 | 0 |
| 5 | 1 | 1 | 0 | 0 | 1 |
| 6 | 0 | 1 | 0 | 1 | 0 |
| 7 | 1 | 0 | 0 | 1 | 0 |
| 8 | 0 | 0 | 0 | 0 | 0 |
In an electronic computer digits may be represented by pulses of voltage or current, or absence of such pulses at appropriate times, or by voltage levels, or current values. In what is known as a Two-State system, such pulses or levels may be standardised to a predetermined value, and the existence of such a pulse, or voltage level, or current value may represent a 1 and the absence of such pulse, voltage level, or current value, may represent a 0.
It may now be seen that the failure of a 1 to arrive at any part of a computer is indistinguishable from 0, so that the resulting sum and carry will, in general, be erroneous. For example, consider Rule 3 of Table 1. If the 1 of Column A fails to appear, then it is read as 0, giving rise to a sum of 1, and a carry of 0.
In order to avoid such errors being unnoticed (indeed, to draw attention their existence) a third state is used together with the two already mentioned. This is a pulse, voltage level, or current value, equal in magnitude but of opposite polarity to that already considered, and this third state is made to represent a 0. Distinction may now be made between a 0 and the absence of a digit, or failure.
Three states are now to be considered. First, the pulse amplitude or current value is zero, or voltage level is at, or about, earth voltage during the quiescent period between digits. Second, the pulse amplitude or current value is of some predetermined magnitude in the positive sense, or the voltage level is above that of earth, again to some predetermined value, to represent the digit ONE. Third, the pulse amplitude or current value, or voltage level, is of opposite polarity to that of the second state just described, and of equal magnitude, to represent the digit ZERO. The absence of a digit state at an instant when there should be one is to be regarded as a fault, and this absence may be caused to operate alarm system, and to stop the computer immediately.
The following Table of the Three-State system replaces Table 1 of the Two-State systems; F failure.
| Rule | Numbers to be added | Result | |||
|---|---|---|---|---|---|
| A | B | C1 | S | C2 | |
| 1 | 1 | 1 | 1 | 1 | 1 |
| 2 | 0 | 1 | 1 | 0 | 1 |
| 3 | 1 | 0 | 1 | 0 | 1 |
| 4 | 0 | 0 | 1 | 1 | 0 |
| 5 | 1 | 1 | 0 | 0 | 1 |
| 6 | 0 | 1 | 0 | 1 | 0 |
| 7 | 1 | 0 | 0 | 1 | 0 |
| 8 | 0 | 0 | 0 | 0 | 0 |
| 9 | F | 1 | 1 | F | F |
| 10 | 1 | F | 1 | F | F |
| 11 | 1 | 1 | F | F | F |
| 12 | 0 | F | 1 | F | F |
| 13 | 0 | 1 | F | F | F |
| 14 | F | 0 | 1 | F | F |
| 15 | 1 | 0 | F | F | F |
| 16 | 0 | 0 | F | F | F |
| 17 | F | 1 | 0 | F | F |
| 18 | 1 | F | 0 | F | F |
| 19 | 0 | F | 0 | F | F |
| 20 | F | 0 | 0 | F | F |
| 21 | 0 | F | F | F | F |
| 22 | F | 0 | F | F | F |
| 23 | F | F | 0 | F | F |
| 24 | 1 | F | F | F | F |
| 25 | F | 1 | F | F | F |
| 26 | F | F | 1 | F | F |
| 27 | F | F | F | F | F |
The first eight rules are the same as in Table 1. The remainder cannot be distinguished from rules of corresponding weight within the first eight by a Two-State system. Examination of the table will reveal certain rules.
1st. The S digit is the same as one of the input digits if the other two are alike, each to each, and conversely, if the two input digits are dissimilar, then the S digit differs from the 3rd input digit.
2nd. The S and C2 are complementary except when all three input digits are alike.
3rd. The various combinations of input digits may be grouped into four complementary pairs, when it will be seen that the corresponding sum and carry digits also are in complementary pairs.
If an electronic reversing switch can be devised, it is apparent that the first rule may be obeyed. Fig.1 shows, schematically, such a circuit.
If a signal, say the A digit signal, is applied to such a circuit, and the switches operated by signals B and C, to the right for zero and to the left for a one, then the resulting signal at S will be the sum digit. This circuit will therefore obey the first rule given above. To comply with rule 2 a similar type of circuit may be devised. This is shown in Fig. 2.
In the circuit of Fig.1, the signal passed to the switch operated by C1 is a zero if A and B are alike (0 + 0 = 0 and 1 + 1 = 0) and conversely, is a one if A and Bare unlike. (0 + 1 = 1 and 1 + 0 = 1) Now, if we make this signal operate the first switch of Fig.2, (indicated by the symbol AB) the signal passed on to the second switch wili be the same as S if A and B are alike, and the opposite if A and B are unlike.
Similarly, B and C1 signals are compared in another switch circuit, and the resulting signal applied to operate the second switch of Fig.2. It may now be seen that if B and C1 are dissimilar, because the second switch will connect the output C2 to the left hand input, which is the reverse of S, the carry digit will differ from S, no matter what the relative values of A and B. Similarly, if A and B differ, the output at C2 will be the reverse of S, whatever is the result of the comparison of B and C1. But if A and B are similar and B and C are similar, i.e. A, B and C are all alike, then the C2 digit will be the same as the S digit.
If now, a pulse system is envisaged, in which positive pulses represent ones, and negative pulses represent zeros the circuit of Fig.3 represents a schematic diagram of a suitable arrangement of transformers and switches.
In Fig.3., the arrow head indicates the switch to be operated by a voltage B, C, etc. as the case may be, the tongue being considered driven downward by a one signal, and upward by a zero signal.
Electronic circuits to operate in fractions of a microsecond can be derived using diode clamp circuits or ring-bridge modulators, for example.
The first successful adding circuit working digitally with positive and negative pulses, at TRE consisted of four ring-bridge modulators, and one pair of diode clamps. This combination provided an economy of diodes over a circuit consisting entirely of diode clamps, the other components remaining approximately constant. This circuit, although logically sound, is uneconomic in practice, and further thought was given to the problem.
Another logical circuit was devised, but this also was considered to be too expensive in valves, and it did not entirely obey primary conditions that no output signal may be generated unless, and until, all three input signals are present in the adding unit. At this stage, circuit ideas were seen to be drifting towards matrix systems, using valves originally, then resistive matrices with valve attachments. These circuits were designed to satisfy all the conditions and rules given above, and the latest arrangement appears to provide all the necessary conditions with a reasonable economy of components.
This circuit consists of a matrix of resistances. The elements of the matrix can be deduced from the mathematical rules to be obeyed. Since the rules occur in complementary pairs, all eight permutations may be dealt with by using four matrix units.
In order to be able to deal with the high frequencies concerned, the three digits to be added are applied as voltages to three resistors with a common low impedance junction.
In a Two-State system, it is sufficient to add the three input signals in a network which may be indicated by the equivalent circuit of Fig.4.
Attached at X is a circuit which has two final outputs, one is the sum output, and the second is the carry output.
Assume for the purposes of explanation, that current inputs are connected to A, B, and C. Then the current outputs from X may be represented as shown in Fig.5.
The circuit attached at X can be so arranged that (a) the output from sum will be ONE unit for rules 1, 4, 6 and 7, and ZERO for rules 2, 3, 5 and 8, and (b), that the output from Carry will be ONE unit for rules 1, 2, 3 and 5, and ZERO for rules 4, 6, 7 and 8.
It will be seen from Table 2, that Rule 9 for example, would give the result as rules 2, 3 and 5, and is therefore indistinguishable from them in a Two-State system.
Now consider the output from X (Fig.4), if the inputs A, B and C are connected to a Three-State system.
A single matrix of the type shown in Fig. 4 is capable of distinguishing two of the permissible conditions from among the 27 possible conditions. If now, the paraphase of the A signal is connected to the point A of Fig.4. then rules 2 and 7 will set up the conditions of Fig. 6, rules 1 and 8, It is therefore possible to use a second matrix to distinguish rules 2 and 7 from among the 27 possible conditions. Similarly, by applying the paraphrase of signal B to the point B of Fig.4, rules 3 and 6 may be so distinguished from among the 27 possible conditions, and by connecting the paraphrase of signal C to the point C of Fig,4, a fourth matrix may be used to distinguish rules 4 and 5 from among the total 27 conditions.
A method of distinguishing the existence of 3 units at the point X of Fig.4 is as shown in Fig.7.
The anode of diode or crystal D1 (Fig.7) is connected to a source of constant voltage d. The resistance R of Fig. 7 is connected to a source of current and is of such a magnitude that 2½ units of current will be drawn through D1.
Now consider sources of current to be connected to the points A B and C, and that Rule 2 of Table 2 applies. From Fig.6 we see that the current at point X of Fig.7 is plus ONE unit. This current will pass down resistance R, leaving 1½ units of current through the diode or crystal D1.
Again, consider the application of current to the three points A B and C such that rule 9 of table 2 applies. We now see iron Fig.6, that 2 units of current will flow at point X of Fig. 7, This current will flow through resistance R of Fig. 7, leaving ½ unit through diode or crystal D1.
If, now, rule 1 of Table 2 is supposed to apply, we see from Fig. 7, that 3 units of current will flow at point X of Fig. 7, and of these, 2½ will flow through Resistance R, and ½ unit will flow through diode or crystal D2 to the circuit connected to point Y of Fig.7. It is possible, therefore to arrange that no current passes from the point X to the point Y unless rule 1, and only rule 1, of Table 2 applies.
Similarly, rule 8 can be distinguished from among the 27 possible rules, by a circuit as shown in Fig.8.
In order to deal with rules 2 to 7, further pairs of circuits as those of Figs. 7 and 8 may be used. The inputs, corresponding to A B and C of Figs. 7 and 8, are Co-A, B, C for rules 2 and 7, A, Co-B C for rules 3 and 6, and A, B, Co-C for rules 4 and 5. (Co-A voltages are exact paraphrase voltages of A voltages). All the conditions set up by rules 9 to 27 will fail to pass any current through diodes or crystals D2 and D4, and will therefore not cause any output to be provided by a circuit connected to Y or Y1 of Figs. 7 and 8 respectively.
The conditions giving rise to rules 1 to 8 must occur in such a manner that only one rule is obeyed at any given instant. It is therefore possible so to arrange that a common circuit is connected to points Y and Y1 of the eight distinguishing circuits. Fig. 9 shows a complete circuit, in principle. The two values V1 and 2 are connected together in such a way that only one condition of stable equilibrium can exist when no signals are applied to the input terminals A, B, C etc. The diodes D4 and D2, and all corresponding diodes are arranged to be biassed-off, and therefore are the equivalent of very high resistances (megohms). No current can therefore pass through them. The control grid of V1, also, passes no current, and there can be no current, therefore, through the feed-back resistor Rβ, since diodes D5 and D6 are biassed-off. Hence the control grid of V1, and the Cathode of V2 are at the same potential. By suitable arrangement of the values of the resistors connecting the positive supply to the anode of V1, the anode of V1 to the grid of V2, from the grid of V2 to the negative supply, and from the cathode of V2 to the negative supply, the two valves are made to operate at appropriate values of current. The Control grid of V1 will then rest at a voltage of Vg, (say).
The voltages d2 and d1 are then arranged to be such that
(d1 + d2) /2 ≈ Vg and d2
d1 ≈ 2 volts
This arrangement ensures that the diodes D2, D4 and corresponding diodes, are biassed off.
When signals are applied to the terminals A B C etc. so that current is made to pass point Y of Fig.7 or Y1 of Fig.8, as described earlier, this current is drawn partly through resistance R, thereby ensuring an output from the point Out (Fig. 9) and partly through the appropriate diode D5 or D6, when the amplitude of the output at Out will be limited to a predetermined value.
It is now necessary to arrange to obtain the appropriate output values to suit the input values, according to the rules 1 to 8. Examination of Table 2 will reveal the fact that, except for rules 1 and 8, the S output and the C2 output are of opposite polarity. If, therefore, the output from one is reversed, the result is the output of the other so long as arrangements are made to accommodate rules 1 and 8. With this fact in view, consider the following circuit arrangement.
The resistance networks at the left hand side of Fig. 9 may be re-drawn as a matrix as in the upper part of Fig. 10. The numbered points of this matrix are to be regarded as joined to the correspondingly numbered points of the diode circuit.
The configuration of the matrix is determined by the rules. The necessary output from the Carry output terminal is first considered, and each rule is examined in turn. Because of the reversal of the phase of the signal through the amplifier circuit, the polarity at the grid of the amplifier has to be opposite that of the output from V2. The connections of the matrix for each, rule is then so determined as to provide the requisite input to the grid of V1.
The output from the cathode of V2 is then taken to a paraphase amplifier and is, with the paraphase output, the input C and Co-C of the next digit of the numbers being added, and so on along the whole number, starting from the least significant figure.
In order to obtain the sum output, which is, for rules 2 to 7 inclusive, the exact opposite of the carry output, the latter is passed into a diode gate circuit, similar to those connected to the matrix, and thence into an amplifier and cathode follower output stage. To accommodate rules 1 and 8, the matrix elements labelled 9 and 10 of Fig.10 are connected to the correspondingly numbered points on the diode gate just mentioned, and the relative magnitudes of the currents from the matrix and from the carry-output are so arranged that for rules 1 and 8, the current from the matrix over-rules that from the carry-output, and for rules 2 to 7, the current from the carry-output over-rules that from the matrix. Table 3 shows that this is possible.
| Rule | Matrix element no 9 | Matrix element no 10 | Carry output to diodes | Sum input | Sum output |
|---|---|---|---|---|---|
| 1 | -3 | -3 | +2 | -1 | 1 |
| 2 | -1 | -1 | +2 | +1 | 0 |
| 3 | -1 | -1 | +2 | +1 | 0 |
| 4 | +1 | +1 | -2 | -1 | 1 |
| 5 | -1 | -1 | +2 | +1 | 0 |
| 6 | +1 | +1 | -2 | -1 | 1 |
| 7 | +1 | +1 | -2 | -1 | 1 |
| 8 | +3 | +3 | -2 | +1 | 0 |
| Units of current | digit |
It will be seen that the last column of Table 3 agrees with the S column of Table 2. In this case, the problem of Faults does not arise, since if the carry output fails, and thus causes a false answer to appear in the sum output, the fact that there is no carry signal is sufficient to cause a failure signal to be given in the checking circuits of the equipment. If one of the diodes of the input circuit of the sum amplifiers fails, and so prevents the necessary current to be passed to the amplifier, no sum output signals will be generated, again bringing into play the failure signals of the checking system.
Critical examination of the input to the sum amplifier will reveal the fact that a false signal may be generated from the two inputs A and B unless suitable precautions are taken. This is due to the fact that the requisite signal value at the input to the amplifier is ± 1 unit. The value of the current delay would then have to be ½ unit. But, if the carry signals are late in arriving, as in the more significant digit positions, then it is possible to get 2 units of input signal, one from each, A and B. To avoid this difficulty, the current delay is maintained at 2½ units, the extra 2 units required to overcome this, by the signal, being obtained from the carry output via the two extra pairs of diodes connected to lines 9 and 10 of Fig.10.
In this way, it is ensured that no spurious signal is obtained from the sum output.
